Models and heursitics for design space exploration of 3D Networks-on-Chips (NoCs) in technology-heterogeneous 3D System-on-Chips.

The design space exploration of 3D NoCs with asymmetry is rather challenging due to the technology heterogeneity present. An optimization of the interconnect design is an open research topic. Here, possible solutions are proposed.

As soon as our publication is accepted, we'll link it here. It includes a comprehensive ddescription.

A mixed integer linear program for the design space exploration is saved. It covers several sub problems and even comprises the popular dimension ordered routing. The description of the formulae as such will be published soon. We use CPLEX as optimizer, which offers academic licenses.

Jan Moritz Joseph: [email protected]

• Dr. Ing. Jan Moritz Joseph
• Dominik Ermel