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Verilog to Routing -- Open Source CAD Flow for FPGA Research

Home Page: https://verilogtorouting.org

License: Other

CMake 0.03% Makefile 0.40% Verilog 34.68% Python 4.03% Shell 0.78% Perl 0.32% C 1.74% C++ 55.97% Yacc 0.64% Lex 0.21% HTML 0.07% JavaScript 0.23% CSS 0.01% Dockerfile 0.01% Nix 0.01% Cap'n Proto 0.02% Tcl 0.09% SystemVerilog 0.29% Ruby 0.01% TeX 0.46%

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