For undergraduate course Computer Organization in NCTU,2017 Spring

only including codes for laboratory section

use 32 bit ripple carry adderas the funfdamantal part to build up the ALU

implemented a single clock cycle cpu with arithmetic operation & branch

build an CPU capable of R/W with memory and additionaly,implemented Jump&Jump return instructions

implementing a simple version 5-stage pipelined CPU, with forwarding& branch pridiction mechanisim

Simulate cache behaviors by C/C++ style cache simulators to understand the performance difference between different cache architectures.