howerj / forth-cpu Goto Github PK

The longest journey begins with a single step.
I git cloned this repository, and am busy trying to understand and document the file embed.c
So I will put all of my comments here in this issue.

So the easiest place to start was the mainloop. The comments on literal, ALU, jump were hugely helpful.

next comment, there are a whole lot of variables, like T, which are not commented.
I assume that T is Top Of Stack. Ny advice would be to at least comment, them or better yet
make them a bit longer. Tos is quite common in the forth community. For other, less often used, I would go with something longer. dataStack, returnStack, etc.

It has been so long since I have done C. There are lots of bitwise c operators. I have to look them up. Good to comment those for those coming from Forth, or other languages.

Not quite sure if I should comment in the source code. There was also an annotation tool I once saw, where one could comment on the code, without editing the original file.

Maybe next I will go back to the forth-cpu docs, and see what all the operands are. Then I know better what the code does.

The Nexsys a7 supports an SD card. We just need a file system, or object database to run on it.
Does anyone know of a good Forth library to use.
And while we are at it, can anyone recommend a good multi tasking library.

So I have decided to use forth-cpu/embed.c and forth-cpu/embed.fth as my forth interpreter. They include a model of a stack cpu. Most other forths are optimized for register machines. So yours is closer to the hardware. Both of those files were updated 2 months ago, the files over on embed/embed were updated 16 months ago. These are newer.

But there is some good documentation in
https://github.com/howerj/embed/blob/master/embed.fth

This issue is just a reminder to copy it over to this repository, or if someone is new to this project,
to go and read it over there.

Is there a way to generate blk-file only containing instructions for a very small program:
1 $4006 !
I've been experimenting a bit with embed (from the embed repo) but have not yet figured out if it is possible or not.
Thank you for sharing this project!

The Nexsys 3 is no longer available.
The Nexsys 4 is end of life. It has been renamed the Nexsys a7.
Only $265 at Diligent, but soon to be discontinued.
https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/

They recommend the Nexsys a7.
https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start

Once the new tool chain is in place, it would be great if the software were upgraded to support the Nexys a7.

There is an excellent resources section at the bottom of the README.md
Having chosen social isolation, I am a bit bored, so I thought I would clean it up a bit.
In a private email exchange, I mentioned the visible script tag at the end of the readme, and
@howerj replied:

That's sort of intentional, I tend to put that little bit of (mostly CSS) at the end of my markdown files so when they are converted to HTML it renders it how I like when using things like pandoc or the original markdown script. Unfortunately GitHub does not take it into account. Thanks for letting me know though.

Turns out when you read the readme.md source code there are even more links listed there, not displaying on github.

Not quite sure what I should do next.

And while I am mentioning things., I took a look at the fpga board for this, not that I am anywhere near buying one, but it does appear to be no longer available.

The best I have seen in the J1 community. It is very helpful to newbies like me.

I assume that your hardware is done with the same meticulous attention to detail.

A couple of points. You have 5 bits for instruction selection. The J1 has 4. Wait a minute. Where did that extra 5th bit come from? I can read the J1 docs and source and figure it out, but it would be good to know up front what the difference is from the J1.

And since you have 5 bits, you could have 32 instructions, why did you stop at 21?

Secondly, people are flooding into Verilog, but you are using VHDL. I suspect that there are good reasons for it. It would be great to read a “Defemse Of VHDL.” Why do you prefer it to Verilog?

The J1 has the stacks in registers and single clock cycle access to memory. I think that you take two clock cycles to access memory. The reasons for that difference with the J1 would also be most interesting to read.

And it would be very helpful if you would state the clock speed, and resources consumed. Lots of data points paint a picture. The MeCrisp Ice, the HX8K version was very helpful in that they stated that they had a multiplier, but it brought the speed down to 36Mhz. Such data points are hugely useful to people like me trying to figure out which way is up. It helped me understand that the J1 is so fast, because it has almost no math functions. Remove the plus function, and it would be even faster!

I see that you have made a lot of progress since I last looked at this many years ago. Good work.

The C graphical simulator is also unique and most important.

And I love how your cpu tightly integrates into the board.

Projects like this are so important. There is not just one J1 processor, there are a family of processors, validating the concept.