mtkCPU is as simple and as clear as possible implementation of RiscV ISA in Amaranth HDL. There is one main file cpu.py, that is including specific units (i.a. decoder, adder etc.)

• implements basic ISA rv32i
• Machine mode and User mode
• traps and interrupts
• CSR registers support
• optional Virtual Memory System - allows for memory translation in User mode
• Debug Module - can connect openOCD and GDB, compatible with Risc-V Debug Spec
• bsp (board specific files) generation - based on RTL code it generates proper .h and .cc files

The design was tested on ice40 FPGA on the iCEBreaker board.

See Quick Start Page and find out how simple it is to deploy fully functional mtkCPU with one command! We provide one-liner that generates a bitstream with Block RAM memory initialized with a specified .elf's content!

• pure-assembly unit tests (more than 80 tests present, each instruction covered)
• single-block testbenches
• co-simulation with openOCD and GDB testing Debug Module
• randomized tests (arithmetic and MMU) using riscv-dv framework from Google

pip3 install .
pytest -x -n4 mtkcpu/tests/

For more information about how tests work, please refer to that file.

Amaranth HDL is a Python framework for digital design, it can compile either to netlist understandable by yosys or Verilog code (that you can place and route using vendor tools, e.g. Vivado)

• Language guide
• Robert Baruch's introduction
• LambdaConcept's Step by Step
• Robert Baruch's refreshed RiscV playlist

Some parts of mtkCPU were inspired by minerva CPU parts (LambdaConcept's property).