hamsternz / artyetherenttx Goto Github PK

Hi, thanks for your great work.

I get this error, when Vivado tries to place the design:

[Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK100MHZ_IBUF] >

CLK100MHZ_IBUF_inst (IBUF.O) is locked to IOB_X1Y76
 clocking (PLLE2_ADV.CLKIN1) is provisionally placed by clockplacer on PLLE2_ADV_X0Y1

The above error could possibly be related to other connected instances. Following is a list of 
all the related clock rules and their respective instances.

Clock Rule: rule_pll_clklds
Status: PASS 
Rule Description: A PLL driving any number of IOBs must be placed within the same clock region
 clocking (PLLE2_ADV.CLKOUT0) is provisionally placed by clockplacer on PLLE2_ADV_X0Y1
 and clock_fwd_ddr (ODDR.C) is locked to OLOGIC_X0Y56

Is this only a problem for me or do I have to do something more than open the project in Vivado to get it to work?

Greetings

Hi @hamsternz . I want to send data to a pc via ethernet with the arty and I have found your controller and it's fantastic. But I don't know where do I have to put the data that I want to send