Can't use SWD on BTT SKR Mini E3 V2.0 about stm32f1xx HOT 4 CLOSED

SWCLCK is driven low here, the 2 second delay could be added there? hal.delay_ms(2000, NULL);

from stm32f1xx.

Yes, that works as advertised. SWDIO (PA13) is still driven low. I don't see a reference to that pin anywhere. It seems like driving it low is a default action.

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It seems like driving it low is a default action.

It is high level on my boards running grblHAL - with different board maps. I do not have a SKR board so cannot easily debug - must be bad code somewhere. Related to the TMC issue?

from stm32f1xx.

The problem is the bootloader. Once the bootloader is removed (overwritten), you can connect and debug.
For me, ST-Link devices (official and clones) did not "want" to connect, no matter what I tried.
I tried de-initting the pins, and then also setting SWD enable and/or JTAG enable in AFIO_MAPR. For what it's worth, I placed the following code in board_init() in btt_skr_mini_e3_2.0.c:

#ifdef RELEASE_SWD_PINS
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_14|GPIO_PIN_13);
//    __HAL_AFIO_REMAP_SWJ_NOJTAG();
    __HAL_AFIO_REMAP_SWJ_ENABLE();
#endif

I also removed C30, the reset timing cap, to try to improve the reset timing with "connect_under_reset" options.
Before I could learn what else the problem could be, I tried a Segger J-Link. It connected immediately, the bootloader was gone, and I was debugging.

Mind you, the board does not support SWD and USB communication at the same time. (Unless you modify the board. I connected GPIO PB5 to the gate of U7 to pull D+ high, and modified the code in board_init() appropriately.)

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