Thank you for your amazing chip!
It's really a powerful chip, my jaw dropped only tinkering the PSG+PCM sections, far from grasping any sense of the whole chip and what it can do.
But during the mocking about, there has been questions back of head that I always hesitate to ask.
Why the PWM respond linearly to values.
Why there's no a different seed/algorithm for noise generation.
Why signed value for PCM.
Why 48.88Khz?
I just assuming there's already an answer floating on the internet and move on, by chance this topic got brought up in a discord bantering https://discord.com/channels/547559626024157184/629903991794434048/1161984652538544138
And evidently, there is no answer as to why the PSG section is it and what it is based on.
There have been discussions about the possibility of FULL AY-8910 compatibly or MOS 6581 compatibly is main driving force.
But I check all datasheets about the AY-8910 MOS 6581 and even Atari POKEY
TI SN76489 and Phillps SAA1099, I can not determine any of them related to VERA PSG.
Internet deep dive resulting nothing.
Could you share some lights on how you went about designing the PSG section, what're the decisions you have to do?
However, also in the discussion, we discovered there are some possible improvements that might be very helpful to further improve the PSG section while costs little to noting.
VERA PSG Fork mode
a. use the highest PWM bit to flip the pulse wave to cover higher than 50 duty cycle.
b. add a different seed/algorithm for noise generation.
c. making duty-cycle logarithmically responses to the PWM value.( optional )
d. a possibly new register or a magic number to write to switch this new mode ON or OFF to remaining compatibly.
e. cap off the pulse width from 6.25 to 50%(or possibly 93.75%) (to free one PWM bit)
If lose one bit on the PWM value and use the bit to flip the phase of the wave to cover 50-99 duty-cycle the resulted precision of PWM is acceptable.
The 75% PWM value is pretty widely used on Ricon 2A03 compositions to make sure the two waves will not "ADD UP" among other fun things!
The ??PWM(value 00) to 6.25PWM(value 04) is most likely not to be very useful in most compositions.....
I know some will jump to use these values right after reading this, but still very little.
As such, it might be sensible to cap it off in the F mode leaving rage to the values that are useful.
The default seed for LFSR noise gen is some what meh, and it can not recreate some of the 2A03 SFX.
The logarithmically response is a way employed by Furnace tracker to making the audio changes with little value change.
This mainly fights the physical and phycological characteristics of our human ears and how we preserves the PWM.
For example, a ??PWM(value 00) to 12.5PWM(value 08) sounds almost the same and almost too unpleasant to use, and 33PWM to 48.5PWM a nontrained person could not tell much difference.
However, the 12.5PWM to 33PWM is a much more drastically change at a higher rate also than mentioned range.
As such, making the making duty-cycle logarithmically responses to the PWM value can make the PWM quickly glide though the ??PWM to 12.5PWM rage, slowdown the changing rate of 33PWM to 50PWM.
This is so rare of a thing that most of the VST expects you to mod it however you like by custom pattern and leave it linear response.
Like I said, very optional.
Personally tho, I think these PSG functions has already been considered and then discarded during the designing.
Could you tell me if I'm right about this?
But just in case it's not, would you consider adding these fetures?
I know how hard it is to design FPGA and how the system is done and how there's little room left on the FLASH or LUTs.
But hey, the VERA FX also is out under the same terms.
Thank you for your time and considerations.
Willhem.