Hi,

My understanding about how the ARM memory model works (but I'm far from an expert on this topic) regarding host to device DMA transfers is the following. The AXI4-Lite control interface of the AXI-DMA is device memory, so writes to its registers are not reordered by hardware. However, the buffer we write in DDR sits in normal memory. Writes to normal memory can be reordered among themselves and also with respect to writes to device memory, if I remember correctly. This means that when we write data to the buffer to perform an H2D transfer and then we write to the AXI-DMA registers to set up and start this transfer, there is no guarantee that the writes to DDR have been observed by the hardware by the time that the writes to the AXI-DMA registers are observed. In theory, this means that the AXI-DMA could potentially start reading data from DDR that hasn't been written yet.

In other applications I've done that controlled the AXI-DMA from userspace, I used a dmb instruction before writing to the registers of the AXI-DMA to configure an H2D transfer, in order to ensure that all the writes to the DDR buffer have been observed before proceeding with the set up of the AXI-DMA. I don't know if there is an easy to way to do this with stable Rust. I googled a bit and all the solutions I saw required nightly.

In practice this is not very important, because not including the barrier is unlikely to give problems. Typically the ARM is much faster in writing to DDR than the AXI-DMA is reading it, so it won't happen that the AXI-DMA will manage to fetch the data before the writes done by the ARM have been observed by the DDR, specially when the buffers that are transferred are not very small.

This crate is certainly working well for me without a barrier, but it might be good to keep these ideas for the future.

By the way I don't know what is the technically correct solution for D2H transfers regarding barriers. I've never done anything special in my applications in this case.

Atm, we use a DMB barrier to make sure that DMA writes are completed before launching the transfer. There is also a DSB barrier. I'm not sure if it matters or if one would be the better choice in terms of performance.

https://stackoverflow.com/questions/15491751/real-life-use-cases-of-barriers-dsb-dmb-isb-in-arm