frehwagen / mega65-core Goto Github PK

A lot of places need fixing to make the pipeline work as expected.

In the original implementation the F018 chip (DMagic) was able to address the first 1MB of the RAM by offering 4 bits for bank addressing as part of the DMAT.

The MEGA65 specific implementation of F018 adds DMAT independent io registers to extent the addressable range.

D704: megabyte level bank of DMAT address
D705: megabyte level bank of DMA source address
D706: megabyte level bank of DMA dest address

This approach uses same bank for source/dest fall all DMAT in chained operation. This enables addressing of the full address space.

The F018A/B adds own support for addressing up to 8MB by rearranging some bit of the DMAT.

F018 DMAT has 11 bytes, F018A/B DMAT has 12 bytes. A sub command has been introduced before the original MOD LO at offset 9.

DIR has been moved to command byte offset 0 (bit 4 source direction, bit 5 dest direction)
MOD,HOLD has been moved to the new introduced sub command (bit 0 source MOD, bit 1 source HOLD, bit 2 dest MOD, bit 3 dest HOLD)

MEGA65 need support for F018A/B, so support latest ROM's.

Because MEGA65 should support old and new ROMs and the kickstart implementation is based on old F018, the implementation at startup should be F018 compatible.

The F018A used status register bit 0 (D703, bit 0 chained) set to 1 to signal it is a F018A. This is used by some ROM's to check if the hardware is F018 or F018A compatible. The MEGA65 will stick with this behaviour even if the real F018B discontinued this flag. In addition the MEGA65 implementation enables to write to D703 to make bit 0 settable to enable F018A/B compatible mode.

Basically after startup of the MEGA65 to be used with late 1991 ROMs

POKEDEC("D703"), 1

enabled F018A/B support and make the ROM to operate properly without PROGRAM MANGELED errors etc.

The F018A/B mode for MEGA65 still supports D704/5/6 mega byte addressing register, it adds the given value from the registers and the bank given in the DMAT.

The side register and the control register for the head side should be not backed by the same internal register. The control register seem to hold the current status, the side register is used for the next sector operation. xemu separates both internally, GEOS driver implementation had some strange workaround that is the result of the registers not separated in the FPGA implementation.

The BCD clock is not served, so time doesn't count up.

Central GEOS time presented in most desk top applications show only the static initial time.

In later ROM's it seems that the TI$ BASIC variable is backed by the BCD time as well, SLEEP is not working anymore with the later ROM's of 1991.