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VHDL simulation model for PADAUK PDK microcontrollers
Looks like instruction takes 2 clock cycle to execute. So 1T means iHRC/2. With 16Mhz crystal cpu is executing 8Mips.
Based on appnote PMC-APN008 http://www.padauk.com.tw//upload/ApplicationNote/APN008_PMS150B_PMS154_user_guide_v003_EN.pdf.
When trying to make
the example, I get the error:
../../hdl/pdkpwmg.vhd:99:21:error: unit "pulsesync" not found in library "work" sync: entity work.pulsesync
On the following line, there's a mismatch on the data width.
I've just learned about this project so I don't know what this exactly does, but it throws errors.
fppa-pdk-emulator-vhdl/hdl/pdk14.vhd
Line 565 in 9dc957e
I don't see that function (signextend15) being used anywhere else. Can it be reduced to 11 bits like so?
function signextend11(a: in wordtype) return unsigned is
variable r: unsigned(10 downto 0);
begin
r(7 downto 0) := a;
r(10 downto 8) := (others => a(7));
return r;
end signextend11;
Thanks!
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