Motorola 68000 16-bit computer
Simple 68000 based 16-bit computer. Just for fun
Folder Structure:
/rtl/verilog Glue logic in Verilog HDL. This replaces a earlier schematic that was using 74 series logic for generating control signals, address decoding, dtack circuity, watchdog monitor and vectored interrupts. Using a CPLD for glue logic eliminates alot of chips, and allows for easily updating or fixing the circuitry with just programming the CPLD.
Currently it relies on a external Power on Reset circuit. Implement the logic in the glue logic
Need to fix symbols and footprints so they are contained within the project, and no references to weird local libraries
In order to support DMA hardware, the CPU bus buffers must be tristated when the CPU releases control of the bus. The CPU releases the bus when ~BGACK is asserted on the rising edge of ~AS
Need extensive simulations of the glue logic top level
Optimize pin placement to reduce routing clutter in PCB layout.
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