Issue Summary

• Type: Enhancement
• Category: Example
• Priority: Medium
• Release Version: 2017.03

Development Environment

• HOST OS
  Windows 10, 64Bit
• TOOLCHAIN
  ARC GNU 2017.03.
• BOARD
  EMSK 1.1
• ARC CORE
  EM6

Enhancement

Wifi name and code should be notified to users about their location,though I know they are in
/board/board.h,they are hard to be found by users from scratch.
For instance:

Extra Comments

Wifi name and password is located in /board/board.h,please be sure the wifi git is correctly
detached before the test.

Issue Summary

• Type: Enhancement
• Category: Device HAL
• Priority: High
• Release Version:

Complex use-case usually requires IRQ priorities tuning according to the specific time constraints.
Since setting IRQ priority needs the knowledge of the particular device IRQ line numbers that is normally hidden by HAL, it is reasonable to add the new HAL API call to reuse the information from device description structure.

Please see code below, this is the example of the possible IRQ priority control command implementation for I2C driver:

1. the new command ID definition in device/ip/ip_hal/inc/dev_iic.h:

             /**
              * Set the required IRQ priority level
              * - Param type : int32_t
              * - Param usage :
              * - Return value explanation :
              */
             #define IIC_CMD_SET_IRQ_PRIO           DEV_SET_IIC_SYSCMD(18)

2. IRQ priority setting call (this call might be shared and declared outisde the I2C driver code, for example, as a macro) and the new command handler in device/ip/subsystem/iic/ss_i2c_master.c

             /* an inline procedure that sets the IRQ priority */
             Inline void ss_iic_set_irq_priority(uint32_t vector, uint32_t priority)
             {
                    _arc_aux_write(0x40b, vector);          /*IRQ_SELECT*/
                    _arc_aux_write(0x206, priority);        /*IRQ_LEVEL*/
             }

             <...>

             /* ...and finally adding the new command handler */
              int32_t ss_iic_master_close(SS_IIC_MASTER_DEV_CONTEXT *ctx)
              {
             <...>
                            case IIC_CMD_SET_IRQ_PRIO:
                                    val32 = (uint32_t)param;
                                    ss_iic_set_irq_priority(ctx->int_err, val32);
                                    ss_iic_set_irq_priority(ctx->int_rx_avail, val32);
                                    ss_iic_set_irq_priority(ctx->int_tx_req, val32);
                                    ss_iic_set_irq_priority(ctx->int_stop_det, val32);
                                    break;
             <...>
             }

Issue Summary

• Type: Question
• Category: ARC HAL | Example
• Priority: Medium
• Release Version: 2017.12

Bug

Development Environment

• HOST OS
  Windows10 , 64Bit

• TOOLCHAIN
  ARC GNU 2017.09.

• BOARD
  EMSK 2.2

• ARC CORE
  EM7D.

Question

Hello！I want to use a few GPIO devices, and I want to set different interrupt priority for them. However, I can only find this function:

arc_int_pri_set(INTNO_GPIO, INT_PRI_MAX)

It seems that all the GPIO devices can only be set as same priority. So, I want to ask if there is any other way to set interrupt priority.Thanks!

Issue Summary

• Type: Question
• Category: Device HAL
• Priority: Medium

Question

Is there any method to use the onboard WiFi module on HSDK? I wonder if there will be any driver provided, THX.

Issue Summary

• Type: Question
• Category: Device HAL
• Priority: High
• Release Version: Specified version such as 2016.05 or All

Development Environment

• HOST OS
  Ubuntu 16.04

• TOOLCHAIN
  ARC GNU 2018

• BOARD
  IoTdk

• ARC CORE
  EM9D.

Question

I want to use I2C ports in Iotdk board, however, I don't know how to use it. I referred to the ARC IoTdk documentation, seeing that in 2x18 extension header, there are I2C0 and I2C1 ports

So, I used DFSS_iic_0_id, and connected my I2C ports to I2C0. Below is my implementation. And, it turned out that I always got "Write Fail" command, and the program would be stuck at ov7670_iic->iic_write(&send_data, 1); I don't know how to fix it? Is my iic_id wrong? Thanks

#include "embARC.h"
#include "embARC_debug.h"
#include "embARC_error.h"
#include "stdio.h"
#define OV7670_IIC_ADDR  0x42
#define OV7670_CHECK_EXP_NORTN(EXPR)       CHECK_EXP_NOERCD(EXPR, error_exit)

DEV_IIC_PTR ov7670_iic = NULL;

static uint8_t seq1[] = {
	0x11,
	0x03
};
int main(void) {
    int ercd = E_OK;
    ov7670_iic = iic_get_dev(DFSS_IIC_0_ID);

    OV7670_CHECK_EXP_NORTN(ov7670_iic!=NULL);
  
    ercd = ov7670_iic->iic_open(DEV_MASTER_MODE, IIC_SPEED_STANDARD);
    ercd = ov7670_iic->iic_control(IIC_CMD_ENA_DEV, (void *)OV7670_IIC_ADDR);
    ercd = ov7670_iic->iic_control(IIC_CMD_MST_SET_TAR_ADDR, (void  *)(OV7670_IIC_ADDR));

    if ((ercd == E_OK) || (ercd == E_OPNED)) {
        EMBARC_PRINTF("Init DONE!\n");
        ov7670_iic->iic_control(IIC_CMD_MST_SET_NEXT_COND, (void*)(IIC_MODE_STOP));
        ercd = ov7670_iic->iic_write(seq1, 2);
        if(ercd == E_OK || ercd == E_OPNED) {
            EMBARC_PRINTF("Write Success\n");
        } else {
            EMBARC_PRINTF("Write Fail\n");
        }

        uint8_t send_data = 0x11;
        uint8_t *REG_data;

        ov7670_iic->iic_control(IIC_CMD_MST_SET_NEXT_COND, (void*)(IIC_MODE_RESTART));
        ov7670_iic->iic_write(&send_data, 1);
        ov7670_iic->iic_control(IIC_CMD_MST_SET_NEXT_COND, (void*)(IIC_MODE_STOP));
        ov7670_iic->iic_read(REG_data, 1);

        EMBARC_PRINTF("Read %2x\n", *REG_data);
    } else {
        EMBARC_PRINTF("Read fail\n");
    }
    
error_exit:
        return ercd;
}

Issue Summary

• Type: Bug
• Category: Example
• Priority: Medium
• Release Version: 2017.03

Bug

Development Environment

• HOST OS
  Windows 10, 64Bit

• TOOLCHAIN
  ARC GNU 2017.03.

• BOARD
  EMSK 1.1

• ARC CORE
  EM6.

Bug Description

When I run the udma example(located at example->baremetal->udma),my putty console shows me the bug message (part of the message are listed below):
default cpu exception handler
exc_no:2, last sp:0x10008834, ecr:0x00020000, eret:0x10002b24
I try to change the ram into external ram by rewriting MARCRO
#define REGION_ROM EXT_RAM//ICCM
#define REGION_RAM EXT_RAM//DCCM
in appl_mem_config.h ,but the problem still exits.

Issue Summary

• Type: Bug | Enhancement
• Category: BSP | Example | Documentation
• Priority: Low
• Release Version: 2017.03

Bug

Development Environment

• HOST OS
  Windows & Linux

• TOOLCHAIN
  MWDT & ARC GNU

• BOARD
  AXS103

• ARC CORE
  ARCHS36

Bug Description

There is no clear statement about supported AXS103 firmware version.

Enhancement

Add clear statement in documentation about what firmware version is supported.

Issue Summary

• Type: Bug
• Category: Example
• Priority: High
• Release Version: 2018.12

Bug

Development Environment

• HOST OS
  Ubuntu 18.04.2 LTS 64Bit

• TOOLCHAIN
  ARC GNU 2018.09.

• BOARD
  HSDK

• ARC CORE
  archs38

Bug Description

There is a bug on line 63 of the <embarc_osp>/board/hsdk/hsdk.mk.

OPENOCD_CFG_FILE = $(OPENOCD_SCRIPT_ROOT)/board/snps_axs103_hs38.cfg

Enhancement

snps_axs103_hs38.cfg should be replaced with snps_hsdk.cfg.

OPENOCD_CFG_FILE = $(OPENOCD_SCRIPT_ROOT)/board/snps_hsdk.cfg

Issue Summary

• Type: Question
• Category: Example | Build System
• Priority: Medium
• Release Version: Specified version such as 2016.05 or All

Question

I want to know how printf() or EMBARC_PRINTF works, and print the output to computer terminal.

Issue Summary

• Type: Documentation
• Release Version: Specified version such as 2016.05 or All

When I read the document of /example/baremetal/simple_bootloader, I found many pictures can't show but image links.

Issue Summary

• Type: Bug
• Category: Example
• Priority: Medium
• Version: 94ee519 at branch feature/iotdevkit

Bug

Development Environment

• HOST OS
  Windows 10, 64Bit

• TOOLCHAIN
  MWDT build (2017.09/rel)

• BOARD
  IOTDK

• ARC CORE
  arcem9d

Bug Description

I've tried examples provided in example folder, however some network example requires ntshell whereas ntshell example is not support for IOTDK yet.

Issue Summary

• Type: Bug
• Category: Example
• Priority: Medium
• Release Version: Latest commit b8d2f7d

Bug

Development Environment

• HOST OS
  Ubuntu 16.04 LTS, 64Bit

• TOOLCHAIN
  ARC GNU 2017.03.

• BOARD
  EMSK 2.3

• ARC CORE
  EM7D.

Bug Description

Take example secret_secure_sid, build with OLEVEL=O0, that will generate couple of push and pop instructions inside function trusted_ops in container2.c, then run the example with command: main -t, you can see something like this:

COM1>main -t
soft interrupt 1 interrupt handler
soft interrupt 1 interrupt handler
Requesting operation from trusted container
protection violation exception at 0x800
cause:memory write violation, parameter:0x44
the region for 0x80005714 is not found
../../../../library/secureshield/core/src/v2/secureshield_int.c: Line 224: halt reason:halt caused by protection violation

0x800 is the address of a push blink instruction, and 0x80005714 is the SP value when trusted_ops is called. It is within the region of _f_bss_container2 and _e_bss_container2. So I think set of this 2 values does not take effect. But when build with O2,

	ctx->initialized = 1;

is fine, that line actually write to background_container's bss region.

When build with O2, all the stack operation's is optimized away, so the example works fine. To reproduce this error with O2, you can add:

Asm("push_s blink\n");
Asm("pop_s blink\n");

inside trusted_ops.

Enhancement

Question

Issue Summary

• Type: Bug
• Category: Example
• Priority: High
• Release Version: 2018.12

Bug

Development Environment

• HOST OS
  Ubuntu 18.04.2 LTS 64Bit

• TOOLCHAIN
  ARC GNU 2018.09.

• BOARD
  HSDK

• ARC CORE
  archs38

Bug Description

When I use the make TOOLCHAIN=gnu BOARD=hsdk BD_VER=10 CUR_CORE=archs38_c0 run command to compile and run the ESP8266 example, the serial terminal displays the following exception.

My ESP8266 module is connected to PMOD_B via serial port.

Issue Summary

• Question
• Example
• Priority: Urgent | High | Medium | Low
• Release Version: Specified version such as 2016.05 or All

The template of workshop

Bug

Development Environment

• HOST OS
  Input the host os name and its version.
  For example, Windows 7, 64Bit | Debian Linux 8.6, 64Bit

• TOOLCHAIN
  Input the toolchain name and its version.
  For example, MWDT L-2016.06 | ARC GNU 2016.03.
  You can also put the compiler version here.

• BOARD
  Input the board name and its version.
  For example, EMSK 2.2 | AXS 103 | nSIM

• ARC CORE
  Input the ARC core name, such as EM7D.

Bug Description

Describe the bug you met in details, and tell us how to reproduce it.
If you want to put some log information here, you can post it here or in github gist.
If there are some screenshots, you can post outside of github, and provide links here.

Enhancement

Describe the enhancement you suggest to add in details.
Explain why you want this enhancement to be added, what are the pros and cons?
Do you have any initial implementation about this enhancement, if yes, post link here.

Question

Input your question in details here.

Issue Summary

• Type: Bug
• Category: Device HAL
• Priority: High
• Release Version: 2017.03

Bug

Development Environment

• HOST OS
  Windows 10, 64Bit

• TOOLCHAIN
  ARC GNU 2017.03.

• BOARD
  EMSK 1.1

• ARC CORE
  EM6.

Bug Description

Before :
#define PMWIFI_MRF24G 0
#define PMWIFI_RW009 1
After,Should be changed into :
#define PMWIFI_MRF24G 1
#define PMWIFI_RW009 0
Since Digilent PMOD WIFI(MRF24WG0MA) is used as Extra Required Peripherals in
/example/freertos/net/httpserver and /example/freertos/net/ntshell

Issue Summary

• Type: Enhancement
• Category: BSP
• Priority: High
• Release Version: 2018.09

Enhancement

Synopsys will introduce a new development system, code named EMDK. This item is opened to track adding the necessary support for this platform

Issue Summary

• Type: Enhancement
• Category: ARC HAL
• Priority: High
• Release Version: All

Enhancement

• ARC processor supports stack check feature, which is useful for stack overflowcheck
• request to add ARC stack check into embARC OSP soon

Issue Summary

• Type: Question
• Category: Example | Documentation
• Priority: Medium
• Release Version: 2017.03

Question

After reading embARC Documentation
I find an file folder being taged as ide_projects listed in the document overview is missing in your latest code release. Did you change this folder's name (if so what is folder's name)or just delete it?

Issue Summary

• Type:Enhancement
• Category: Example
• Priority: Medium
• Release Version: 2017.12

Development Environment

• HOST OS
  Windows 10

• TOOLCHAIN
  ARC GNU 2017.09

• BOARD
  EMSK 1.1

• ARC CORE
  EM6

Question

Is there any example for GPIO ?
(like how to mapped to the defined pmod pin for reading and some for write)

Since I have to connect the EMSK with my custom module. So I need to read and write synchronous with clock through the pmod in EMSK with baremetal development.

Issue Summary

• Type: Question
• Category: Example
• Release Version: Specified version such as 2016.05 or All

Question

Anybody knows how to do memcopy using (uDMA controller) with unaligned source or destination address (single transfer mode)? Most important is descriptor setting.
For example src = 0x0000_4001, dst = 0x0000_5000, len = 256 bytes.

If both src and dst addresses aligned (to 4 bytes boundary) then it has no issue.
I am using ArcEm ver 2 core.
Thanks.

Issue Summary

• Type: Question
• Category: Device HAL | Example
• Priority: Medium
• Release Version: 2017.12

Bug

Development Environment

• HOST OS
  Windows 7, 64Bit

• TOOLCHAIN
  ARC GNU 2017.09.

• BOARD
  EMSK 2.2

• ARC CORE
  EM7D

Bug Description

I have read the "ibaby" example,and i tried to code the gpio interrupt by following the btn interrupt,(embarc_applications/ibaby_smarthome_multinode/src/lamp_node/driver/btn/) ,but my project could not raise the interrupt.

Enhancement

void usart4_init(void)
{
	DEV_GPIO_BIT_ISR bit_isr;
	DEV_GPIO_INT_CFG int_cfg;

	uart4 = gpio_get_dev(EMSK_GPIOUART4_PORT);

	EMSK_GPIO_CHECK_EXP_NORTN(uart4 != NULL);
	if (uart4->gpio_open(GPIO_UART4_MASK) == E_OPNED) {
		uart4->gpio_control(GPIO_CMD_SET_BIT_DIR_OUTPUT, (void *)(GPIO_UART4OUT_MASK));
		uart4->gpio_control(GPIO_CMD_SET_BIT_DIR_INPUT, (void *)(GPIO_UART4IN_MASK));
		uart4->gpio_control(GPIO_CMD_DIS_BIT_INT, (void *)(GPIO_UART4_MASK));
	}
	int_cfg.int_bit_mask = GPIO_UART4IN_MASK;
	int_cfg.int_bit_type = GPIO_UART4IN_MASK;
	int_cfg.int_bit_polarity = BTN_ACTIVE_LOW;
	int_cfg.int_bit_debounce = GPIO_UART4IN_MASK;
	uart4->gpio_control(GPIO_CMD_SET_BIT_INT_CFG, &int_cfg);
	bit_isr.int_bit_ofs = GPIO_UART4IN_MASK;
	bit_isr.int_bit_handler = EXTI1_IRQHandler;
	uart4->gpio_control(GPIO_CMD_SET_BIT_ISR, &bit_isr);
	uart4->gpio_control(GPIO_CMD_ENA_BIT_INT, (void *)GPIO_UART4IN_MASK);
	uart4->gpio_write(GPIO_UART4OUT_MASK,GPIO_UART4OUT_MASK);
error_exit:
	return;
}

Question

By the way,I want to konw is there any example about PWM settings?

Issue Summary

• Type: Bug
• Category: BSP
• Release Version: Specified version such as 2016.05 or All

Bug

Development Environment

• HOST OS: Windows 10, 64bit

• TOOLCHAIN: MWDT L-2017.06

• BOARD: EMSK 2.3

• ARC CORE: Any

Bug Description

FPU and DSP registers are not saved during handling of interrupts and exceptions, This may lead to undefined behavior.
For my case: I have a thread that has a division operation, and there is a vKernelTick which is the ISR of tick timer of freertos port. This interrupt has also a division operation in calling of board_timer_update. MW is optimizing the local variables in case of division and use the accl and acch registers, so if the tick interrupt happens after performing the division operation and before using accl or acch register, there will be a corrupted values in those registers when returning from the ISR where an exception happened and the arc_reset is called.

Enhancement

Adding the following code to INTERRUPT_PROLOGUE and EXCEPTION_PROLOGUE at arc_asm_common.h

#if ARC_FEATURE_FPU_DSP_CONTEXT
	SAVE_R58_R59
	SAVE_FPU_REGS
	SAVE_DSP_REGS
#endif

and the following to INTERRUPT_EPILOGUE and EXCEPTION_EPILOGUE

#if ARC_FEATURE_FPU_DSP_CONTEXT
	RESTORE_DSP_REGS
	RESTORE_FPU_REGS
	RESTORE_R58_R59
#endif

same as SAVE_CALLEE_REGS and RESTORE_CALLEE_REGS.

Issue Summary

• Type: Enhancement
• Category: Documentation
• Priority: Medium
• Release Version: All

Enhancement

Need to add or update documents for new added features.
Need to update pictures.
Depreciated doxygen comments should be removed.
All url links should be checked to ensure the usablity.

Issue Summary

• Type: Bug
• Category: Library
• Priority: High
• Release Version: Specified version such as 2017.03

Bug

Development Environment

• Windows 7, 64Bit

• Compiler Version: ARC GNU, 7.1.1 20170710

• User specific

• EM6

Bug Description

In library secureshield, initialisation of containers .bss and .data sections seems not to be done. In file secureshield_vmpu_arc.c (both v1 and v2), in function vmpu_ac_container the two lines:

memcpy(container_cfg->data_start, container_cfg->data_load_start, VMPU_REGION_SIZE(container_cfg->data_end, container_cfg->data_start));
memset(container_cfg->bss_start, 0, VMPU_REGION_SIZE(container_cfg->bss_end, container_cfg->bss_start));

seem to do nothing because data_end/bss_end is always greater or equal to data_start/bss_start respectively. It seems end/start have been swapped in macro VMPU_REGION_SIZE parameters (typo ?)

Enhancement

Replace the two mentioned lines by:

memcpy(container_cfg->data_start, container_cfg->data_load_start, VMPU_REGION_SIZE(container_cfg->data_start, container_cfg->data_end));
memset(container_cfg->bss_start, 0, VMPU_REGION_SIZE(container_cfg->bss_start, container_cfg->bss_end));

Example is working with this correction.

Issue Summary

• Type: Enhancement
• Category: Device HAL
• Priority: Medium
• Release Version: All

Enhancement

On board flash support quad SPI which could multiply read/write speed.
Add quad SPI may also support future peripherals.

Issue Summary

• Type: Question
• Category: Build System
• Priority: Urgent
• Release Version: metaware_vM-2016.12

Bug

Development Environment

• HOST OS
  Input the host os name and its version.
  For example, Windows 7, 64Bit | Debian Linux 8.6, 64Bit

• TOOLCHAIN
  metaware_vM-2016.12

• BOARD
  nSIM

• ARC CORE
  EM7D.

Bug Description

Enhancement

Question

I tried simply by changing the LCF file to show DDR region from 0x00010000 instead starting from 0, but only the main.dis and main.hex starting address changed to 00001000 but main.bin (which is going to real DDR chip) still holding the address of 0.
Anybody can help with the compile/linker option to achieave this?

Thanks for advise

Issue Summary

• Type: Question
• Category: Device HAL
• Priority: High
• Release Version: Specified version such as 2016.05 or All
• BOARD
  Iotdk

Question

Hi, I wonder if there a simple codes to read pin value without calling gpio_read function. Since if we have to call gpio_read function, the processor would need to allocate a stack for the function, do another of unnecessary things. If there is a way like AVR that accesses the PIN by the below.

I want to have a faster pin access time in IOTDK. Thanks.

uint8_t input_value = PIND&4 // get the input value of pin number 2 at port D

Question

I wonder that if ARC IoTDK can connect webcam and apply image processing?
Is there any sample project or code?

Issue Summary

• Type: Bug
• Category: Device HAL
• Priority: Medium
• Version: 94ee519 at branch feature/iotdevkit

Bug

Development Environment

• HOST OS
  Windows 10, 64Bit

• TOOLCHAIN
  MWDT build (2017.09/rel)

• BOARD
  IOTDK

• ARC CORE
  arcem9d

Bug Description

The TX of UART1 and UART2 are fine but will hang trying to receive any message with interrupt. Seems like signals are unable to be received in UART1&2.

Issue Summary

• Type: Enhancement
• Category: Device HAL
• Priority: Medium
• Version: 94ee519 at branch feature/iotdevkit

Development Environment

• HOST OS
  Windows 10, 64Bit

• TOOLCHAIN
  MWDT build (2017.09/rel)

• BOARD
  IOTDK

• ARC CORE
  arcem9d

Enhancement

The interrupt mode of DFSS I2C driver is supported in current version, but there's no I2C polling mode.

Issue Summary

• Enhancement
• Category: Example
• Priority:Low
• Release Version: 2017.03

Enhancement

When you go to /example/baremetal/arc_feature/udma/main.c,you can find the section "extra comment".In this section,I think supported board version should be noted since it's important for users to tell which device this example can run on.
For instance:

Extra Comments

Please notify that this device supports: boards ver 2.2 or above.

Issue Summary

• Type: Bug
• Category: Library
• Priority: High
• Release Version: 2017.03

Bug

Wrong initial value of variable i in function __do_global_dtors_aux

Development Environment

Ubuntu 16.04 LTS, 64 bit

• TOOLCHAIN
  ARC GNU 2016.09

• BOARD
  EMSK 2.3

• ARC CORE
  EM7D

Bug Description

Line 115 in function __do_global_dtors_aux initialize variable i to wrong value 0, i should start from 1 but not 0, 0 cause processor jump to a random address (in most case address 0) and execute from there, that cause application terminate in a wrong status.

In arc_cxx_startup.c
109 void __do_global_dtors_aux(void)
110 {
111 unsigned int nDtors;
112 unsigned int i;
113
114 nDtors = (unsigned int)__DTOR_LIST__[0];
115 i = 0;
116
117 while (i <= nDtors) {
118 __DTOR_LIST__[i++]();
119 }
120 }
i = 0 should be i = 1

Enhancement

Initialize variable i to 1.

Question

Issue Summary

• Type: Bug
• Category: Documentation
• Priority: Low
• Release Version: 2017.12

Bug

Bug Description

there is a spelling mistake in embARC guide documentation.
location is embarc_osp/doc/documents/middleware/middleware.rst.
line 3 in middleware.rst spelled "Middlwares".
this spelling mistake could be seen signally as it is a title of this
webpage(http://embarc.org/embarc_osp/doc/build/html/middleware/middleware.html).

Issue Summary

• Type: Question
• Category: Example
• Priority:Low
• Release Version: 2017.03

Development Environment

• HOST OS
  Windows 7, 64Bit

• TOOLCHAIN
  ARC GNU 2017.03

• BOARD
  EMSK 2.2

• ARC CORE
  EM7D

Question

I notice that there is an example named embARC C++ support Test. I want to know Whether embARC supports all C ++ syntax or not? So it has supported C/C++ now? But I couldn't find any information about it in the embARC introduction.

Issue Summary

• Type: Bug | Enhancement | Question
• Category: ARC HAL | Device HAL | BSP | OS | Middleware | Library | Example | Build System | Tools | Documentation | Installation | Usability
• Priority: Urgent | High | Medium | Low
• Release Version: Specified version such as 2016.05 or All

Development Environment

• HOST OS
  Input the host os name and its version.
  For example, Windows 7, 64Bit | Debian Linux 8.6, 64Bit

• TOOLCHAIN
  Input the toolchain name and its version.
  ARC GNU 2016.03.

• BOARD
  Input the board name and its version.
  board: iotdk

• ARC CORE
  Input the ARC core name
  Core : EM9D

Question

Input your question in details here.

This is the example of lab6_ble_rn4020. After i run the example code and the program stopped at 0x200034b0 in exc_handler_default (p_excinf=0x80001788)
at ../../../arc/arc_exception.c:332
332 Asm("kflag 1");

Issue Summary

• Type: Bug
• Category: Library
• Priority: High
• Release Version: 2017.03

Bug

Development Environment

• HOST OS
  Ubuntu 16.04 LTS 64 bit

• TOOLCHAIN
  ARC GNU 2017.03.

• BOARD
  EMSK 2.3

• ARC CORE
  EM7D.

Bug Description

Take secret_secure under example/baremetal/secureshield as example, other examples share the same issue.
When build the example using command:
make BOARD=emsk BD_VER=23 CUR_CORE=arcem7d TOOLCHAIN=gnu OLEVEL=O0

In console, any command invoke main cause a exception:

COM1>main -h
soft interrupt 1 interrupt handler
../../../../library/secureshield/core/src/v2/secureshield_sjli.c: Line 121: halt reason:interface @253c0 not found in container 1

But build without OLEVEL=O0 works fine.

The problem is caused by sjli instruction: when invoke sjli instruction, the registers for parameters are set before a call to arc_lock_save (in secureshield_secure_call_exports.h line 103-118), when build with O0, the call to function arc_lock_save is a function call and destroyed r0 and r2, that are the parameters for sjli. When build is O2, gcc optimize the function call out and only generated a clri instruction like this:
81a: 272f 013f clri r4

Enhancement

To make the code independent of optimization level, either move the function call before set of parameter registers or use clri and seti instruction directly.

Question

Issue Summary

• Type: Enhancement
• Category: ARC HAL
• Priority: High
• Release Version: All

Enhancement

Add the basic arc xy memory support in embARC_OSP. XY memory provides higher memory throughput, which is useful for DSP application or other cases

Issue Summary

• Type: Bug
• Category: Library
• Priority: High
• Release Version: 2017.03

Bug

Development Environment

• HOST OS
  All

• TOOLCHAIN
  All

• BOARD
  All

• ARC CORE
  All

Bug Description

In secureshiled.h, struct SECURESHIELD_CONFIG defines mode as a pointer to a 32 bits word:
typedef struct {
uint32_t magic;
uint32_t *mode;

/* protected flash memory region */
uint32_t *secure_rom_start, *secure_rom_end;
/* protected bss */
uint32_t *secure_ram_start, *secure_ram_end;


uint32_t *background_rom_start, background_rom_end;
uint32_t *background_ram_start, background_ram_end;

/* container configuration tables */
uint32_t *cfgtbl_start, *cfgtbl_end;

/* pointers to container configuration tables */
uint32_t *cfgtbl_ptr_start, *cfgtbl_ptr_end;

} EMBARC_PACKED SECURESHIELD_CONFIG;

Unfortunately, in wrapper.s where the structure is actually initialized, a value is written (0 or 1) instead of an address of a 32 bits word. Any dereferencing of the pointer "mode" can lead to a memory access failure (bad memory address or mpu protected address). In our case, in secureshield.c, the following line:
*(__secureshield_config.mode) = SECURESHIELD_DISABLED;
tries to write in ROM at address 0x1 (flash memory) which is not allowed and raises an exception.

Enhancement

Two options are possible:
-Declares "mode" as a 32 bits word but as it resides in secure ROM, it will be constant.
-Actually initialize "mode" with the address of a 32 bits word in secure RAM, the later taking the value 0 or 1. I don't know in this case if it is usefull to store the address in ROM inside SECURESHIELD_CONFIG or better to directly use the variable in secure RAM...

Issue Summary

• Type: Question
• Category: OS | Tools
• Release Version: Specified version such as 2016.05 or All

Question

I have an issue when i enable FreeRTOS awareness in metaware debugger.
it was working fine and all tasks is displayed in debug window, each of them with its function call stack.
now after push and pop 1 more register after r25 in SAVE_CALLEE_REGS and RESTORE_CALLEE_REGS respectively (i.e SAVE_R58_R59, RESTORE_R58_R59) which found in file "arc_asm_common.h" the debugger only shows function call stack of the current running task only, and the other tasks show (symbols not available).

Thanks.

Issue Summary

• Type: Question
• Category: Example
• Priority: Urgent
• BOARD Iotdk

Question

Could you provide the falling edge interrupt example for iotdk board in arduino pin AD0 and AD1? I can't find any example of this. There is one issue here talking about this, but it seems to be for button interrupt. Thanks.

Issue Summary

• Type: Bug
• Category:Example
• Release Version: 2017.03

Bug

Development Environment

• HOST OS
  Windows 7, 64Bit

• TOOLCHAIN
  ARC GNU 2017.03.

• BOARD
  EMSK 2.2

• ARC CORE
  EM7D.

Bug Description

I want to run baremetal_dma_spiflash example but it doesn't work, it just output the working frequency &1000000 and random vlaue 4, then got struck. What went wrong?

Issue Summary

• Type: Question
• Category: Usability
• Priority: Urgent
• Release Version: Specified version such as 2016.05 or All
• BOARD IoTdk

Question

the default baudrate is 115200. However, I want a faster baudrate. I set it to 230400 up to 921600. But none of them work. But I can set it to 38400, and my computer serial works. Is it possible to use the console uart baudrate up to 1M? thanks.

PS: I set the baudrate in iotdk.h file like the below.

#define BOARD_CONSOLE_UART_BAUD			UART_BAUDRATE_921600

Issue Summary

• Type: Question
• Category: Example
• Priority:Low
• Release Version: 2017.03

Development Environment

• HOST OS
  Windows 7, 64Bit

• TOOLCHAIN
  ARC GNU 2017.03

• BOARD
  EMSK 2.2

• ARC CORE
  EM11D

Question

In the user manual of the example, embARC Secondary Bootloader, it says that "For EMSK1.x, bootloader core configuration must be arcem6, for EMSK2.x, bootloader core configuration must be arcem7d. ", But why? It was running successfully when I used the core configuration arcem11d for EMSK2.2.

Issue Summary

• Type: Question
• Category: Example | Usability | Bug
• Priority: High
• Release Version: 2016.1.12 v2.2

Bug

Development Environment

• HOST OS

  Windows 7, 32Bit

• TOOLCHAIN
  ARC GNU 2016.03.

• BOARD
  Input the board name and its version.
  For example, EMSK 2.2

• ARC CORE
  ARC EM7D.

Bug Description

We brought a max30102 module to support the project recently.But the ir led and red led of the module can not be lightened when we connect the four pins(VCC GND SDA SCL) to the board.
We found out some videos about max30102 ,they showed that it works well with some boards,such as STM32 and Ardunio,by connecting the four pins we have mentioned above.

Issue Summary

• Type: Bug
• Category: Library
• Priority: High
• Release Version: 2017.03

Bug

Development Environment

• HOST OS
  Ubuntu 16.04 LTS, 64Bit

• TOOLCHAIN
  ARC GNU 2017.03.

• BOARD
  EMSK 2.3

• ARC CORE
  EM7D.

Bug Description

SECURESHIELD_SECURE_CALL is used to generate call to sjli_secureshield_int_ops for a group of functions defined in library/secureshield/export/src/interrupts.c. The problem is sjli_secureshield_int_ops and sjli_secureshield_sys_ops does not preserver FP register, in stage CLEAR_SCRATCH_REGS it set FP to 0. This is not a critical problem when build with O2, there FP register is not used, but when build with OLEVEL=O0, FP is used to save SP, and restore SP from FP cause SP be set to 0. This can be easily validated by build test_case project with OLEVEL=O0, you will see a exception in the beginning of main function at:

    EMBARC_PRINTF("timer0 interrupt prioirty is:%d\r\n", secureshield_int_pri_get(INTNO_TIMER0));

Enhancement

Save FP to stack in SECURESHIELD_SECURE_CALL.

Question

Issue Summary

• Type: Bug
• Category: Library
• Priority: High
• Release Version: 2017.03

Bug

Development Environment

• HOST OS
  Ubuntu 16.04 LTS 64Bit

• TOOLCHAIN
  ARC GNU 2017.03.

• BOARD
  EMSK 2.3

• ARC CORE
  EM7D.

Bug Description

In secureshield.h line 65 and 66:

uint32_t *background_rom_start, background_rom_end;
uint32_t *background_ram_start, background_ram_end;

A asterisk symbol should be put before background_rom/ram_end to make them pointer.

Enhancement

Question

Issue Summary

• Type: Bug
• Category: Library
• Release Version: Specified version such as 2016.05 or All

Bug

Bug Description

When I compiled secureshiel/secret_normal example, I found that the function secureshield_int_pri_set() in secureshield declarations conflict at the second paramenter
command: make BOARD=emsk BD_VER=23 CUR_CORE=arcem7d TOOLCHAIN=gnu

//the definition is    
//export/src/interrupts.c:176   
int32_t secureshield_int_pri_set(uint32_t intno, int intpri)   
{   
}   

//the declaration is    
//export/inc/secureshield_int_exports.h:41
extern int32_t secureshield_int_pri_set(uint32_t intno, int32_t intpri)    
{    
}

Issue Summary

• Type: Question
• Category: Library
• Priority: High
• Release Version: All

Question

Is ARC able to output clock using PWM interface? For example, like arduino, we can use PWM output and configure it as 8MHz clock. If yes, is there any library we can use since in embarc website, we can’t find any. Thanks

Below is How Arduino configures a 8MHz clock using AVR library.

DDRB|=(1<<3);//pin 11

ASSR &= ~(_BV(EXCLK) | _BV(AS2));

TCCR2A=(1<<COM2A0)|(1<<WGM21)|(1<<WGM20);

TCCR2B=(1<<WGM22)|(1<<CS20);

OCR2A=0;//(F_CPU)/(2*(X+1))

Issue Summary

I want to use ARC iotdk to do some machine learning inference application.
So I reference the example that provided in embarc_osp/example/baremetal/embarc_mli/cifar10_caffe.
There are two files "cifar10_coefficients_chw_big.c" and "cifar10_coefficients_chw_small.c" that list all the coefficients of the convolution layers.
I wonder how to transform the pre-trained model into that coefficient files.
Is there any automation tool or flow could support the transformation?

Development Environment

• HOST OS
  Win10 64 bit

• TOOLCHAIN
  gnu toolchain

• BOARD
  ARC IoTDK

• ARC CORE
  arcem9d

Question

I wonder how to transform the pre-trained model into that coefficient files.
Is there any automation tool or flow could support the transformation?

Issue Summary

• Type: Enhancement
• Category: Tools
• Priority: High
• Release Version: All

Enhancement

Improve CI for better usability
Upgrade Python version