Building a RISC-V CPU Core (LFD111x) is designed for anyone with a technical inclination who is interested in learning more about hardware. Whether you are new to digital logic or are a seasoned veteran, students will take away new skills that can be applied immediately. No prior knowledge of digital logic design is required.

This is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open source development. You will familiarize yourself with a number of emerging technologies supporting an open-source hardware ecosystem, including RISC-V, Transaction-Level Verilog, and the online Makerchip IDE.

LFD111x is a hands-on experience with RISC-V and modern circuit design tools. You will walk away with fundamental skills for a career in logic design, and you will position yourself on the forefront by learning to use the emerging Transaction-Level Verilog language extension (even if you don’t already know Verilog).

By the end of this course, you will learn about: ● Digital logic design (combinational and sequential logic) ● RISC-V (RV32I) instruction set architecture ● Basic CPU microarchitecture ● Transaction-Level Verilog basics ● Makerchip online IDE

Anyone with a technical inclination can successfully complete the workshop. No prior knowledge of digital logic design is required.

You may want to consider first taking Introduction to RISC-V (LFD110x) prior to this course, though this is not a prerequisite.

The lab environment (Makerchip) is entirely online. The only system requirement is a web browser.

This course is designed for anyone with a technical inclination who is interested in learning more about hardware.

As founder of Redwood EDA, Steve Hoover is fostering an open-source silicon ecosystem through numerous technologies including the WARP-V CPU core generator with support for RISC-V. His main focus is design methodology and tools enabled by Transaction-Level Verilog (TL-Verilog), available to all at makerchip.com. He is also the lead developer of the 1st CLaaS open-source framework for cloud FPGAs. Steve holds a BS in electrical engineering summa cum laude from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He has designed numerous components for high-performance server CPUs and network architectures for DEC, Compaq, and Intel.

4-6 hours

• Welcome!
• Chapter 1: Learning Platform
• Chapter 2: Digital Logic
• Chapter 3: The Role of RISC-V
• Chapter 4: RISC-V-Subset CPU
• Chapter 5: Completing Your RISC-V CPU
• Final Exam (Verified Certificate track only)

• https://learning.edx.org/course/course-v1:LinuxFoundationX+LFD111x+1T2021/home