Fekete Balazs Valer's Projects
VHDL Advanced Encryption Standard cores
A recursive modular reduction of mine, that only uses powers of 2 division and modulus calculation.
A commutative hash, that relies on permutations and sums to hinder solving the discrete logarithm problem.
Masking based side channel resistant descriptions.
Matrix computation performance benchmarks.
My way of retrieving continuous distance data of Chinese Remainder Theorem with FFT
An easy to understand implementation of the recursive FFT concept coded in Matlab.
Yet another electrical engineer.
All course files for the Flutter Beginners playlist on The Net Ninja YouTube channel.
A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
A hash based trie data structure, also involving hash map and linked lists.
Generic description of a pipelined matrix multiplier with 4 multiplier threads. It calculates C += A * B'
Montgomery multiplication in number bases that are a power of 2, like binary, hexadecimal, byte-wise etc.
Parameterizable recursive descriptions of high speed adders.
A multi 10Gb/s capable Galois Counter hash module for AES-GCM
A hardware friendly modular multiplication.
Fully pipelined SHA2-256 VHDL description with circular buffers instead of shift registers for low power.
VHDL Secure Hash Algorithm 2 cores
SHA-2 versions working on 64 bits of data: 384 and 512.
Side channel attack simulations
Lightning or Sun burst induced current protection concept.
An open source cross-platform USB stack for embedded system
Karatsuba multiplication with recursive hardware description in VHDL.
VHDL implementation of side channel attack proof Speck cipher.
Basic and fast UDP IPv4 MAC stack written in VHDL
A sinusoidal oscillator based on the Z-transform sine with exponentially changing amplitude.