facebookresearch / deepfloat Goto Github PK

Hello @wickedfoo,
Readme specifies to use python3.x for validating the model. However, there is a memory mapping error while programming the FPGA. Using python2.x solves that issue. However, the fully connected layer has a problem.

Traceback (most recent call last):
File "run_fpga_resnet.py", line 103, in
reference_model=cpu_model)
File "/home/manoj/git/deepfloat/py/validate.py", line 112, in validate
output = fpga_h.forward(input)
File "run_fpga_resnet.py", line 37, in forward
self.output_p = self.model.forward(*dev + (input_p, ))
File "/home/manoj/git/deepfloat/py/fpga_resnet.py", line 209, in forward
x = self.fc.forward(context, program, queue, x)
RuntimeError: Assert failed at /home/manoj/git/deepfloat/cpp/ops/TensorMath.cpp line 217

line 217: CL_ASSERT(a.getSize(1) == b.getSize(0));

PaperPositPETop.sv output unknown state (xxxxx). This is because of the FF in line 27 to line 30 has no reset value, which results makes the input of PaperPositPE to be xx. As a result, qPostAdd become unknown state in the first clock after rst=0, consequently qReg.data. Hence forth the output will be stuck at unknown state.

This is the FF which has no reset value in file PaperPositPETop.sv
always_ff @(posedge clock) begin
aInReg.data <= aIn;
bInReg.data <= bIn;
end

File "run_fpga_resnet.py", line 36
input_p = ext.to_posit(*dev, input)
SyntaxError: only named arguments may follow *expression

Add https://arxiv.org/abs/1811.01721 to readme.

Hello,

I have used your Posit implementation of addition and multiplication as a reference model in my master thesis. During the verification of my code I have found some issues and a possible bug in your implementation.

The first problem is that it is not possible to select ES values bigger than POSIT_WIDTH-3. And looking at the documentation of the numbers there is no restrictions for the ES value. In order to support it in your code I have changed the PositDecode and PositEncode files. But maybe it is also needed to change other files.

The second problem is that there is a bug in the multiplication rounding. The value of the normalTrailingBits is not correct so I have added a line in the PositMultiply module assigning the correct value to the variable. With this change the multiplication results were correct.

Please find attached the three files I have modified. I would like to know if these changes make sense for you or I misunderstood something.

Best regards,

Laura.
PositDecode.txt
PositEncode.txt
PositMultiply.txt

Hi,

I used paper_syn/Wave_PaperLogPETop.sv to simulate PaperLogPETop. All correlated file were included in Wave_PaperLogPETop.sv. I used ncverilog to simulate and met "Multiple drivers to always_comb output variable preRound.data.isZero detected." in LogNumberUnpackedToLogCompact.sv. I used verdi to check corrections of connections (around "preRound") but I can't find them. Can you help me to solve problem.

Best Regards,
Andy Chang