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Amigo 1000 - Conversion of the Amiga 1000 schematic into Verilog 2001 RTL
Amigo - Amiga 1000, in Verilog 2001, from schematic Copyright 2010, Jason S. McMullan The aim of the Amigo is to create a schematic-level capture of the digital components of the Commodore Amiga 1000. My personal reason for this project is to have a functional Verilog simulation that can be used to: * Validate emulators * Convert into FPGA (a la Minimig) * Assist in debugging old Amiga hardware * Regenerate the Amiga 1000 schematic from Verilog The last point seems to be the most important for me. All of the Amiga 1000 schematics I have been able to obtain online are very blurry, almost to the point of unreadability. My hope is that the 'Amigo' will be able to be used to generate a faithful and readable schematic one day. - Jason S. McMullan ==== Progress so far: * Selectable Wishbone cores for emulating the Motorola 68000 - ao68000 (from OpenCores) - True Motorola 68000 emulation, but Icarus Verilog 0.9 appears to hate it. - ucore (from OpenCores) - MIPS32 core, which I am using for debugging under Icarus. - Any other Wishbone complaint 32-bit CPU core should be pluggable, via the 'Motorola_16_to_w32.v' module and a small amount of glue logic for interrupts. * Amiga 1000 Daughterboard logic appears to be complete - $E00000 mirror of $F80000 does not exist, could be due to erroneous PAL logic. Will verify against my reference hardware. Things to do: * Create wrappers for Minimig's OCS cores (Paula, Agnus, Denise), to leverage the Minimig work for Amigo. * Decide upon (for REAL!) whether to make the first pass of the Amigo 1000 a Rev A or a Rev C machine. - This affects mostly the part numbering (ie U6U or U6S for the M68000, etc). - It is most likely I will be doing a Rev A, as that appears to be what I have as my reference hardware. * Finish out the Amigo capture, including pullup resistors, ferrite beads, etc. * Decide what to do about the analog components (ie RGB to NTSC conversion circuity). Icarus Verlog doesn't (as of 0.9.x) support Verilog-AMS, so I may have to put that off.
I really appreciate your great work!
There is just one little thing.
from DAUGCAS.v:
initial ROM01 = 1'b0;
always @(*)
ROM01 <= ROME && _A17 && _WPRO && _SROM && _PRW;
This doesn't match Commodore's documentation, they say _A18 instead of _A17:
ROM01 <= ROME && _A18 && _WPRO && _SROM && _PRW;
See the A1000 "source" files from
https://www.amigawiki.org/doku.php?id=de:parts:pld_download
When I get it right this is the switch signal which switches the WOM to read-only, and disables the BOOT-ROM after the WOM has been written. This should be active only for the memory area from 0xf80000 to 0xfbffff, but it must not be active above 0xfc0000 because that area is used to write the to the WOM?
0xf8 = 1111 1000
where the first '0' is /A18 and not /A17.
When you use /A17 instead of /18, the signal would be active for 0xf80000 to 0xf9ffff and from 0xfc0000 to 0xfdffff.
I'm currently working on Kick-Board like the KUPKE / Golem Kickstart ROM Module, see here:
https://www.bigbookofamigahardware.com/bboah/product.aspx?id=1557
Therefore I needed to understand the WOM mechanism (how to disable it) and I try to understand the PAL equations.
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