H GENG's Projects
save current working directory and cd you back anytime, anywhere
2021年秋季学期 南京大学ICS课程 Lab实验部分
2021年秋季学期 南京大学ICS课程 PA实验部分
my blog (Beta)
A LATEX template of NJU Thesis 2021 Version 南京大学本科生毕业论文LaTex模板 2021版
The best way to write secure and reliable applications. Write nothing; deploy nowhere.
阿拉伯数字转多种中文读法
NJU Virtual Board
templates for nvboard usage
RTL, Cmodel, and testbench for NVDLA
OpenXuantie - OpenE906 Core
Handwritten digit recognition.
echo a random quote every time you start the terminal
一个使用risc-指令集的cpu,五级流水线,forked from ycx122
Stop-To-Ask-Questions-The-Stupid-Ways
lowRISC SystemVerilog Style Guides
A very simple and easy to understand RISC-V core.
Synopsys Design compiler, VCS and Tetra-MAX
Helping you become familiar with powers of 2
Test code for Verilog & System Verilog
Verilator 4.210 User’s Guide. Verilator 4.210 Manual.
templates for verilator and nvboard usage
Verilog AXI components for FPGA implementation