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~/asplos22-hardware-debugging-artifact/hardware-bugbase/d1-buffer-overflow-rsd$ make -j8
echo sources.txt
sources.txt
../../veripass/verilator/bin/verilator -cc -timescale-override 10ps/10ps -Wno-WIDTH -Wno-LITENDIAN -Wno-UNPACKED -Wno-BLKANDNBLK -Wno-CASEINCOMPLETE -Wno-CASEX -Wno-TIMESCALEMOD -Wno-BLKLOOPINIT -Wno-PINMISSING -Wno-ALWCOMBORDER -Wno-VLTAG -trace-fst -trace-structs -comp-limit-syms 0 -assert -trace-max-array 65536 -trace-max-width 65536 -F sources.txt -top-module ccip_std_afu_wrapper --Mdir work
perl: warning: Setting locale failed.
perl: warning: Please check that your locale settings:
        LANGUAGE = (unset),
        LC_ALL = (unset),
        LANG = "en_US.UTF-8"
    are supported and installed on your system.
perl: warning: Falling back to the standard locale ("C").
make -C work -f Vccip_std_afu_wrapper.mk
make[1]: Entering directory '/home/jacy/asplos22-hardware-debugging-artifact/hardware-bugbase/d1-buffer-overflow-rsd/work'
Vccip_std_afu_wrapper.mk:52: /usr/local/share/verilator/include/verilated.mk: No such file or directory
make[1]: *** No rule to make target '/usr/local/share/verilator/include/verilated.mk'.  Stop.
make[1]: Leaving directory '/home/jacy/asplos22-hardware-debugging-artifact/hardware-bugbase/d1-buffer-overflow-rsd/work'
make: *** [Makefile:34: verilator] Error 2

$(MAKE) -C $(RTL_WORK_DIR) -f V$(TOP_MODULE).mk

$(MAKE) -C $(RTL_WORK_DIR) -f V$(TOP_MODULE).mk VERILATOR_ROOT=$(VERILATOR_ROOT)