dreamchenhao Goto Github PK
Name: dreamchen
Type: User
dreamchen's Projects
radar_tools
雷达信号处理工具箱
scopy
A software oscilloscope and signal analysis toolset
srai_hw_accel_windows10_pcie
PCIe based accelerator for VCU1525 with xDMA based on Windows10 and Windows Server 2016 development environment
srslte
Open source SDR LTE software suite
taoquick
a cool QtQuick/qml component library and demo(一套酷炫的QtQuick/Qml基础库和示例)
tbox
🎁 A glib-like multi-platform c library
transceivertoolbox
MATLAB toolbox for ADI transceiver products
verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
verilog-cam
Verilog Content Addressable Memory Module
verilog-dsp
Verilog digital signal processing components
verilog-ethernet
Verilog Ethernet components
verilog-flowgen
Ethernet flow generator framework
verilog-ft245
Verilog FT245 to AXI stream interface
verilog-i2c
Verilog I2C
verilog-lfsr
Fully parametrizable combinatorial parallel LFSR/CRC module
verilog-mersenne
Verilog implementation of Mersenne Twister PRNG
verilog-pcie
Verilog PCI express components
verilog-uart
Verilog UART
verilog-wishbone
Verilog wishbone components
vivado_batch_mode_tool
A tool for those who want to use Vivado's batch mode more easily
vspi
Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter
wishboneaxi
Wishbone to AXI bridge (VHDL)
wradlib
weather radar data processing - python package
xfcp
Extensible FPGA control platform
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