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En este laboratorio se requiere que el grupo de trabajo diseñe, implemente en un HDL y demuestre su funcionamiento con un kit FPGA, un controlador para un sistema de dispositivos de señalización y prevención (semáforo y agujas) para un cruce de vía vehicular - ferroviaria . Este controlador estará basado en una máquina de estados finitos (FSM), además incluirá la lógica combinacional y secuencial necesaria para apoyar a la máquina de estados.

Verilog 14.69% HTML 11.43% C 73.70% Batchfile 0.18%
verilog xilinx fpga spartan hdl finite-state-machine

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