Debtanu Mukherjee's Projects
32-bit Superscalar RISC-V CPU
Verilog Implementation of completely parameterized booth multiplier
This is the Verilog implementation of custom RISC ISA
This is the verilog implementation of DES cryptography
This is a repository containing all the Quartus and NIOS II simulation files and the testcases for EE705 course
This is the verilog implementation of IEEE 754 32 bit floating point multiplier
FPGA implementation of up / down BCD counter
Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.
Lightweight OoO GPGPU
This is the Verilog code for 8085 microprocessor with limited (18) number of instructions
A High-performance Timing Analysis Tool for VLSI Systems
Verilog implementation of a 6-stage pipelined custom RISC processor
rodinia benchmark modified to run with ENZO and pathcu instead of nvcc CUDA compiler
A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
This is a verilog implementation of 4x4 systolic array multiplier