db47h / hwsim Goto Github PK

Omitted output pins are nil.

almost none to be seen !

The new simulation algorithm breaks with loops.

See #16

implement proper benchmarks.

The loop detection implemented in eeb49ed only happens at runtime and identifying components involved in the loop is impossible. This check should be done statically.

It doesn't belong here.

If len(ups) is for example 9 and workers is 8, it will start only 9 / ((9/8)+1) = 4 workers.

Change pins to a full fledged Wire:

type Wire struct {
    value bool
    clk      bool          // clock cycle for value
    src      Updater
    fanout []Updater
}

func (w *Wire) Set(clk bool, value) {
    if w.clk != clk {
        w.clk, w.value = clk, value
    }
}

func (w *Wire) Get(clk bool) bool {
    if w.clk != clk {
        w.src.Update(clk)
    }
    return w.value
}

With wires driving the simulation. Need to find a way to identify a "hot wire" that will trigger the whole simulation.

We could also have a wire trigger a cascading update on Set (by updating all in fanout), but then components would have to keep track of time as well.

When building a PC like this:

bit := Chip("bit", "in, load", "out",
	hl.Mux("a=out, b=in, sel=load, out=mux"),
	hl.DFF("in=mux, out=out"),
)

register16, err := Chip("register", "in[16], load", "out[16]",
	bit("in=in[0], load=load, out=out[0]"),
	bit("in=in[1], load=load, out=out[1]"),
	// ...
	bit("in=in[15], load=load, out=out[15]"))

mux16 := hl.MuxN(16)

pc, err := Chip("counter", "in[16], inc, load, reset", "out[16]",
	register16("in[0..15]=rin[0..15], out[0..15]=out[0..15], load=rload"),
	hl.OrNWay(3)("in[0]=inc, in[1]=load, in[2]=reset, out=rload"),
	hack.Inc16("in[0..15]=out[0..15], out[0..15]=iout[0..15]"),
	// increment out?
	mux16("a[0..15]=out[0..15], b[0..15]=iout[0..15], sel=inc, out[0..15]=inc[0..15]"),
	// load ?
	mux16("a[0..15]=inc[0..15], b[0..15]=in[0..15], sel=load, out[0..15]=ld[0..15]"),
	// reset ?
	mux16("a[0..15]=ld[0..15], sel=reset, out[0..15]=rin[0..15]"),
)

There's a wire loop. More details to come.

This would allow using bus notation for buses with both in and out pins

For example, a lookahead carry unit has 5 carry pins, one input, four output:

Chip("LCU", "p[4], g[4], c[0..0]", "p, g, c[1..4]", hw.Parts{
    // ...
}) 

For custom components, what if we did something like this:

type Mux8 struct {
    In  [8]int `hw:in`
    Sel int    `hw:in`
    Out [8]int `hw:out`
}

func (m *Mux8) Update(c *Circuit) {
    // ...
}

// Along with a Component interface
type Component interface {
    Update(c *Circuit)
}

And use reflect to get the specs of a part. Chip.mount could then instantiate parts as needed and init their input/outputs.

The idea is to make it doable, NOT to move Chip().

This will require exporting a few methods in Socket, mostly.

This is a matter of perspective: It makes much more sense from a Go perspective (in which case Socket must go in favor of some more aptly named interface)

type NewFn func (w Wires) // or Wiring or ?

But then we have Circuit and other Chip...

This would make it easier to test both builtin components and more complex chips in one go.

The current implementation is flawed:

A circuit allocates a bunch of components across several worker goroutines. At each step:

• Workers are triggered to start by a write to their channel
• Workers update their allocated components
• Workers wait for the next start trigger.

This sort of works, but it's pretty bad performance wise. The problem is with the simulation implementation:

The simulator is built as an array of individual wires (think [stripboard]). It works like a double-buffer with a "current state" array and a "next state" array. At every tick of the simulation:

• all components are updated:
  • input states are read from the "current state" array
  • output states are written to the "next state" array
• the "current state" and "next state" arrays are swapped.

So this cannot be fixed by removing Step and allow the workers to run for a full clock cycle since the wire buffer needs to be swapped after each update of all components.

Solutions:

1. Split the simulation into several circuits with an external clock and clocked interconnect components.
2. Implement a more advanced simulation algorithm. If, and only if there's one that can be implemented efficiently in a concurrent manner.

Followup on #16

Need to find a way to access the const *Wires

Started in daced20

This will make major api changes easier as it will allow ignoring hwlib until the changes are complete and fully tested.

That's easily done and will allow changing a few strings to int internally.

With Chip now taking strings as arguments and the addition of MakePart, shortened names like IO, IOs can now be turned back into something more meaningful.

Consider Update(clk int) instead of Update(clk bool); this would eliminate the need to reset all pin's clk in Circuit.update

See #21 (comment)

• DMux4Way
• DMux8Way
• Mux16
• Mux4Way16
• Mux8Way16
• Or8Way