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Currently MSIM is able to print an alert when (CPU) exception is raised.

The idea behind this issue is to explain why the exception was raised. While it is often possible to determine the reason from various status registers, explicit explanation might help beginners understand the issue more quickly.

Below are to concrete examples where such information would was clearly missing and students were unable to quickly find out what were the actual reasons for the exception.

1. When TLB refill is raised it might be worth stating that there is no such item or that there is such an item but with different ASID.
2. Page fault (on RISC-V) should explain whether the reason is missing page table entry or missing SUM bit when supervisor tries to access user pages.

The documentation regarding RICV-V TLB default size mentions a Kilo-TLB and Mega-TLB size, which is a remnant of previous implementation.

Typing add <Tab><Tab> should print list of known devices. Currently, nothing happens.

This does not work in 1.3.8.5 either but according to the old tutorial this used to work at some time in the past. Certainly a nice feature.

• The example for adding a keyboard does not contain the interrupt number.
• Document now interrupt is delivered (i.e., to the first CPU)
• Document how the number is used (mip on RISC-V and cause on MIPS)

The current implementation of the printer device (dprinter) flushes output inside printer_step4k, that is, only every 4096 simulator steps. Possibly, this was done to improve simulation speed, but as a result the print output is not visible when single stepping using the gdb interface. This is not a problem in the msim interface, because it uses the same output as the machine and flushes during command prompts.

(I can do the change, the reason for the ticket is I'm not sure there aren't other reasons for the delayed flush.)

Calling cpu cp0d cause is much more user friendly than cpu cp0d 13.

In interactive mode, msim should first print version and then suggest to use the 'help' command. When the 'help' command is used, it should also somehow give hint about existence of device commands.

Hi everyone,
I would like to report an issue with wrong documentation, section System commands -> break here.

Documentation shows syntax for break: break address type, which is incorrect for msim 2.2.0, where break syntax is this:

[msim] help break
Add a new physical memory breakpoint
Syntax: break <addr> <cnt> <type>
        <addr> memory address
        <cnt> count
        <type> Read or write breakpoint

The documentation then describes parameters address and count instead of type.

MSIM is built as a deterministic simulator but for detecting race conditions in student assignments a bit of randomization might help.

This might include tiny changes to the counter registers so that timer interrupts are not coming always at the same time. Perhaps there are other sources (destinations) of randomness?

When MSIM is killed (e.g. via timeout from scripts), it breaks terminal configuration. input_back() should be called from signal handlers too.

The csrrd dump of RISC-V CPU is rather long and for debugging purposes in our courses most of the counters are not really needed (and only clutter the view).

It might make sense to split this into two commands and remove the performance counters from the basic dump.

echo "add ddisk disk" | ./msim

Terminates with

<msim> Alert: Configuration file "msim.conf" not found, skipping
<msim> Alert: MSIM 2.1.0
<msim> Alert: Entering interactive mode, type `help' for help.
[msim] add ddisk disk
<msim> Error: Missing parameter "register block address"
Segmentation fault      (core dumped)

dumpdev prints the following for a rwm device:

[  name  ] [  type  ] [ parameters...
mem        rwm        [Start    ] [Size      ] [Type]
00000000000            0 none

Rather it should be:

[  name  ] [  type  ] [ parameters...
mem        rwm        [Start    ] [Size      ] [Type]
                      00000000000            0 none

The csrrd and tlbrd are named after the rd command, which stands for "register dump".
In this way csrrd would read "control and status register register dump" and tlbrd would read "translation look-aside buffer register dump"

I would propose to change these commands to csrd and tlbd.
This would also be more consistent wrt. the MIPS commands, where the TLB dump is also named tlbd.

There seems to be a difference in handling translations between virtual and physical addresses in MSIM 1.3.8.5 and current HEAD when ERL bit is set.

Not yet sure which version behaves correctly, perhaps the old MSIM treats the condition for Cache error and ERL=1 for any exception.

Copying this as-is from a TODO file (there is no context whether this refers to emulated memory, some part of some student assignments or MSIM's use of malloc):

add debug features
 - memory allocation
 - first and last block check
 - show all allocated memory blocks
 - check for unallocated memory at the end of the program or at the free function call
 - allocation information (function, file and the line number)

When running bats system tests with version Bats 1.2.0-dev all the tests are skipped.

Output:

$ bats tests/system/basic.bats 
bats: ~/msim/tests/system/common.bash.bash does not exist
bats: ~/msim/tests/system/common.bash.bash does not exist
bats: ~/msim/tests/system/common.bash.bash does not exist
bats: ~/msim/tests/system/common.bash.bash does not exist
bats: ~/msim/tests/system/common.bash.bash does not exist

5 tests, 0 failures, 5 not run

I think this problem is on line 3 of tests/system/basic.bats: load "common.bash".
It seems bats adds an extra .bash at the end of the filename.

Removing the .bash from the load fixes this problem for me.
(changing the line to load "common")

The implementation is actually there (cp0_dump_all()) but this function is never called.

In progress as a student project.

It would be useful if in some mode (perhaps we can abuse -t for this?) MSIM would warn about possibly wrong use of TLB.

• Set TS field (TLB shutdown) in DS (diagnostic status) of status register to 1 if more entries match (and possibly print a warning?)

  • This should help especially for situations when TLB is used for the first time and contains ASID 0 for all entries
  • Should conform to section 4.1, paragraph Multiple Matches that states: If more than one entry in the TLB matches the virtual address being translated, the operation is undefined. To prevent permanent damage to the part, the TLB may be disabled if more than several entries match. The TLB-Shutdown (TS) bit in the Status register is set to 1 if the TLB is disabled.

• Perhaps warn if multiple physical frames are accessible via different virtual addresses?

  • This should be enabled with some specific flag only as it is completely fine that this happens for shared memory but usually indicates a bug in toy kernels.

Header file /usr/include/bits/limits.h in Alpine (tested in Docker on alpine:latest (b2aa39c304c2)) defines PAGESIZE.

This shadows the variable in device/cpu/riscv_rv32ima/cpu.c.

Fix is to rename this variable to lower case or something similar.

Use the defined constants for bit shifts in bit operations (e.g. in cp0_status_ie).

Following should raise an error and second device should not be added.

echo -e "add dr4kcpu one\nadd rwm one 0x0\ndumpdev" | ./msim

Instead, dumpdev prints the following:

[  name  ] [  type  ] [ parameters...
one        dr4kcpu    R4000
one        rwm        [Start    ] [Size      ] [Type]
00000000000            0 none

This bit shall signal the current state of the device (operation in progress) and could be used for simple implementations without a need for interrupt handling.

This option should enable monitoring register changes in the assembler (during trace) but it does not do anything at the moment. As a matter of fact, the boolean variable associated with this flag is never read anywhere in the code.

Code can use special instruction to enter interactive mode. When run from script, this usually creates issues (simulation may appear to hang when in fact it is just waiting for input). We should have a way to avoid this:

• an extra command line switch that would make any attempt to enter interactive mode exit the simulator
• checking whether we have interactive input using isatty
• ... ?

If the status register is badly set (cp0_status_ksu == 3) MSIM may terminate on assertion in either convert_addr_kernel32 or convert_addr_kernel64 because of ASSERT(CPU_KERNEL_MODE(cpu)); (inside cpu.c, called from convert_addr).

It should probably be better to throw an exception (perhaps excCpU for Coprocessor Unusable) to allow the user debug the problem instead of aborting forcefully.

[Reproducible with Kalisto if one of the mfc0 $status is commented out in the context switch code.]

This msim.conf should fail when 'dir' is a directory:

add ddisk drive 0x10000000 1
drive generic 1M
drive save dir

But it continues the execution.

Tab completion does not work for second parameter.

Example session follows:

<msim> Alert: Configuration file "msim.conf" not found, skipping
<msim> Alert: MSIM 1.4.0
<msim> Alert: Entering interactive mode, type `help' for help.
[msim] add dcpu cpu
[msim] cpu <TAB>
bd     br     break  cp0d   goto   help   id     info ...
[msim] cpu b<TAB>
bd     br     break  
[msim] cpu bre<TAB>

Sub-command is not completed when it is the only option.

This is regression from 1.3.8.5 where this worked.

The RISC-V privileged specification states: "Instruction address-translation and protection are unaffected by the setting of MPRV." on page 23.

MPRV is a bit in mstatus CSR which enables memory translation of memory loads and stores for M mode.
We currently translate all memory accesses when MPRV is set, which is incorrect behavior for instruction fetches, which should not be translated.

[msim] cpu tr 0
M-mode Bare translation

OK: 0x080 => 0x000000000

Instead of padding the virtual address to 8 hex digits, it puts a 08 between 0x and the address.