SystemVerilog code for HDMI 1.4a video/audio output on an FPGA.

Most free and open source HDMI source (computer/gaming console) implementations actually output a DVI signal, which HDMI sinks (TVs/monitors) are backwards compatible with. To support audio and other HDMI-only functionality, a true HDMI signal must be sent. The code in this repository lets you do that without having to license an HDMI IP block from anyone.

1. Take files from src/ and add them to your own project. If you use hdlmake, you can add this repository itself as a remote module. Note that hdlmake may not resolve altera_gpio_lite properly, since it does not define ALTERA_RESERVED_QIS during Quartus project resolution.
2. Other helpful modules for displaying text / generating sound are also available in this GitHub organization.
3. Consult the simple usage example in top/top.sv.
4. See hdmi-demo for code that runs the demo as seen the demo GIF.
5. Read through the parameters in hdmi.sv and tailor any instantiations to your situation.
6. Please create an issue if you run into a problem or have any questions. Make sure you have consulted the troubleshooting section first.

• Altera
• Xilinx (untested but should work)
• Lattice (unknown)

• 24-bit color
• Data island packets
  • Null packet
  • ECC with BCH systematic encoding GF(2^8)
  • Audio clock regeneration
  • L-PCM audio
    • 2-channel
    • 3-channel to 8-channel
  • 1-bit audio
  • Audio InfoFrame
  • Auxiliary Video Information InfoFrame
  • Source Product Descriptor InfoFrame
  • MPEG Source InfoFrame
    • NOTE—Problems with the MPEG Source Infoframe have been identified that were not able to be fixed in time for CEA-861-D. Implementation is strongly discouraged until a future revision fixes the problems
  • Gamut Metadata
• Video formats 1, 2, 3, 4, 16, 17, 18, and 19
• VGA-compatible text mode
  • IBM 8x16 font
  • Alternate fonts
• Other color formats (YCbCr, deep color, etc.)
• Support other video id codes
  • Interlaced video
  • Pixel repetition
• Special I/O features
  • Double Data Rate I/O (DDRIO)

You'll need to set up a PLL for producing the two HDMI clocks. The pixel clock for each supported format is shown below:

The second clock is a clock 10 times as fast as the pixel clock. Even if your FPGA only has a single PLL, the Altera MegaWizard (or the Xilinx equivalent) should still be able to produce both. You can avoid using two different multiplication factors, with the DDRIO feature, which only requires the second clock to be 5 times as fast.

Both audio bitrate and frequency are specified as parameters of the HDMI module. Bitrate can be any value from 16 through 24. Below is a simple mapping of sample frequency to the appropriate parameter

• Limited resolution: some FPGAs don't support I/O at speeds high enough to achieve 720p/1080p
  • Workaround: use DDR/other special I/O features like I/O serializers
  • Workaround: Altera FPGA users can try to specify speed grade C6 and see if it works, though yours may be C7 or C8. If it doesn't work, try enabling DDRIO.
• FPGA does not support TMDS: many FPGAs without a dedicated HDMI output don't support TMDS
  • You should be able to directly use LVDS (3.3v) instead, tested up to 720x480
  • This might not work if your video has a high number of transitions or you plan to use higher resolutions
  • Solution: AC-couple the 3.3v LVDS wires to by adding 100nF capacitors in series, as close to the transmitter as possible
    • Why? TMDS is current mode logic, and driving a CML receiver with LVDS is detailed in Figure 9 of Interfacing LVDS with other differential-I/O types
      • Resistors are not needed since Vcc = 3.3v for both the transmitter and receiver
    • Example: See J13, on the Arduino MKR Vivado 4000 schematic, where LVDS IO Standard pins on a Cyclone 10 FPGA have 100nF series capacitors
• Poor wiring: if you're using a breakout board or long lengths of untwisted wire, there might be a few pixels that jitter due to interference
  • Make sure you have all the necessary pins connected (GND pins, etc.)
  • Try switching your HDMI cable; some cheap cables like these I got from Amazon have poor shielding
• Hot-Plug unaware: all modules are unaware of hotplug
  • This shouldn't affect anything in the long term; the only stateful value is hdmi.tmds_channel.acc
  • You should decide hotplug behavior (i.e. pause/resume on disconnect/connect, or ignore it)
• EDID not implemented: it is assumed you know what format you want at synthesis time, so there is no dynamic decision on video format
  • To be implemented in a display protocol independent manner
• SCL/SCA voltage level: though unused by this implementation...it is I2C on a 5V logic level, as confirmed in the TPD12S016 datasheet, which is unsupported by most FPGAs
  • Solution: use a bidirectional logic level shifter compatible with I2C to convert 3.3v LVTTL to 5v
  • Solution: use 2.5V I/O standard with 6.65k pull-up resistors to 3.3v (as done in J13 on the Arduino MKR Vivado 4000 schematic)
    • To investigate: why do they do this, and does it work at all?

Dual-licensed under Apache License 2.0 and MIT License.

• HDMI Intel FPGA IP Core: Stratix/Arria/Cyclone
• Xilinx HDMI solutions: Virtex/Kintex/Zynq/Artix
• Artix 7 HDMI Processing: VHDL, decode & encode
• SimpleVOut: many formats, no auxiliary data

If you know of another good alternative, open and issue and it will be added.

These documents are not hosted here! They are available on Library Genesis and at other locations.

• HDMI Specification v1.4a
• EIA-CEA861-D.pdf
• DVI Specification v1.0
• IEC 60958-1
• IEC 60958-3
• E-DDC v1.2

• Mike Field's (@hamsternz) demos of DVI and HDMI output for helping me better understand HDMI
  • http://www.hamsterworks.co.nz/mediawiki/index.php/Dvid_test
  • http://www.hamsterworks.co.nz/mediawiki/index.php/Minimal_DVI-D
• Jean P. Nicolle (fpga4fun.com) for sparking my interest in HDMI
  • https://www.fpga4fun.com/HDMI.html
• Bureau of Indian Standards for free equivalents of non-free IEC standards 60958-1, 60958-3, etc.
• Glenwing for links to many VESA standard documents