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zignig

hapenny's Issues

SOC it to me!!!

Just to be clear...

The intent of the hapenny is to have a riscv target on an FPGA written in Amaranth.

  • In it's nude form it MUST fit on a iCE40HX-1k with a little bit of spare logic for designs.
  • It SHOULD include a rust target for writing control code

It's Alive ! tiny_bx

Managed to port the new version of the cpu to the tiny_bx board.

https://github.com/zignig/hapenny/blob/main/tinybxtestbox.py

Changed the PLL and the oversampling on the UART was turned down to 4. It compiled and uploaded onto the board running at 40Mhz. I can then connect to the FTDI and there seems to be characters echoing. Hooray!

I have been digging into risc-v and rust and managed to cobble together a runtime thing. (https://github.com/zignig/patina)

Is it possible to release the tiny-bootloader (which I assume is rust) ?

Automapping getting closer , also have a python monitor client...

[22:07:21] INFO     Building Patina                                                          tinybxtest.py:205
           INFO                                                                           fabric_builder.py:44
           INFO     Device Scan                                                           fabric_builder.py:45
           INFO     --------------------                                                  fabric_builder.py:41
           INFO                                                                           fabric_builder.py:42
           INFO     BasicMemory - 12                                                      fabric_builder.py:63
           INFO     BootMem - 8                                                           fabric_builder.py:63
           INFO     BidiUart - 1                                                          fabric_builder.py:63
           INFO     bus width 12 (hw)                                                     fabric_builder.py:68
           INFO     bus extra bits 2 (hw)                                                 fabric_builder.py:69
           INFO     total width 14 (hw)                                                   fabric_builder.py:70
           INFO     --------------------                                                  fabric_builder.py:41
           INFO                                                                           fabric_builder.py:42
           CRITICAL BasicMemory                                                           fabric_builder.py:83
           CRITICAL BootMem                                                               fabric_builder.py:83
           CRITICAL BidiUart                                                              fabric_builder.py:83
           CRITICAL                                                                       fabric_builder.py:91
           INFO     --------------------                                                  fabric_builder.py:41
           INFO                                                                           fabric_builder.py:42
           CRITICAL MemoryMap(name='BasicMemory')     00-------------, 15                 fabric_builder.py:94
           CRITICAL MemoryMap(name='BootMem')         010000---------, 15                 fabric_builder.py:94
           CRITICAL MemoryMap(name='BidiUart')        0110000000000--, 15                 fabric_builder.py:94
           INFO     --------------------                                                  fabric_builder.py:41
           INFO                                                                           fabric_builder.py:42
           CRITICAL BasicMemory     0       8192                                          fabric_builder.py:98
           CRITICAL BootMem         8192    8704                                          fabric_builder.py:98
           CRITICAL BidiUart        12288   12292   

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