Design Goal

• Simple as possible

Spec

• 8 bit data bus
• 8 bit ALU with following function
  • add, subtract
  • and, or, xor
  • rotate left, rotate right
• 3 scratch register
• 8 bit instruction
• 0, 1 or 2 operand instruction
• 1 or 2 word instruction.
• Hardwire Control Unit

Diagram

Explanation

1. Fetch instruction from RAM by
   1. Load MAR with instruction address in IP
   2. Load IR with content from RAM
   3. Increment IP
2. Decode instruction in IR
3. Execute instruction
4. Repeat step above until hit HALT instruction

Data

Arithmetic

Bitwise

Rotate Left

Rotate Right

Control flow

See Assembler directory for example program.

All the constrains are based on Basys 3 Artix-7 FPGA Board, which you might have to adjust it if you use other FPGA board.

This project is a part of CPE223 Digital Electronics and Logic Design. Department of Computer Engineering, King Mongkut's University of Technology Thonburi.