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View Code? Open in Web Editor NEWCollection of various iCE40 FPGA designs
Collection of various iCE40 FPGA designs
Known bug:
Some of the characters may have wrong outputs. They follow the below regularity:
All wrong outputs caused by some 0 bits turning into 1 & Most of them happened in lower bits;
The bit before the wrong bit is always 1.
E.g. 0001->1111; 0100->1100; 0101->0111; 1101->1111
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