buhuixie Goto Github PK

sysycompiler

PKU course: Compiler Principles' lab, a sysy compiler, including sysy to eeyore, eeyore to tigger and tigger to riscv

tiger

虎书编译器，毕业设计

tiger-1

exercise for tiger complier

tiger-c

Compiler practice written in C.

tiger-compiler

tiger compiler reference to Modern Compiler Implementation in C (Tiger Book).

tigercompiler

Implementation and Exercises in Modern Compiler Implementation in C.

tomasulo

An out-of-order execution algorithm for pipeline CPU, implemented by verilog

toy-cpu

toy_cpu

A MIPS32-like five-stage pipeline soft-core toy cpu.

ucas-calab-mycpu_axi_verify

计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15

ucas-compilation-assignment-1

编译程序高级教程，大作业一

vector-norm-processor

Verilog Implementation of a Vector L2 Norm Processor

vector_processor

Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor

verigpu

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-harvard-cpu

Verilog implementation of various types of CPUs

vliw-architecture-design-project

A simple VLIW architecture designed and implemented in Verilog.

vnlp

Vector Norm List Processor in Verilog, Digital Design II Project

zap

ZAP is a superpipelined processor compatible with legacy ARM binaries. Copyright (C) 2016-2022 Revanth Kamaraj(krevanth)