Z80 CPU and Memory Module

• Overview
  • Specifications
• Assembly Instructions
• Hardware Documentation
  • Schematic and PCB Layout
  • Input/Output Ports
  • Connectors
  • Bill of Materials
  • CPLD Fuse Map
• Release Notes
  • Changes
  • Known Issues
• Red Tape
  • Licensing
  • Trademarks

Z80-512K is an RC2014*-compatible module, designed to run RomWBW firmware including CP/M, ZSDOS, and various applications under these OSes. Z80-512K combines functionality of the following RC2014* modules on a single module, thus saving space on the backplane:

• Z80 CPU Module
• 512k ROM 512k RAM Module
• Clock and Reset Module

In addition to these functions, Z80-512K includes programmable CLK2 clock divider, support for battery-backed SRAM, power failure NMI generation, and a watchdog.

Minimal CP/M computer system can be built using Z80-512K module, a backplane, and a serial port module, such as Z80 SIO or MC68B50 ACIA. For configurable baud rate settings, it is recommened to use serial modules that can use CLK2 as a clock, for example Steve Cousins' SC132 or SC104 modules. Additional storage module is not required, since RomWBW utilizes part of ROM and SRAM for ROM and RAM disks respecitvely, but a Compact Flash module can be added for additional storage.

• Processor: Zilog* Z80 CPU (CMOS version - Z84C00)
• Memory: 512 KiB battery-backed SRAM, 512 KiB Flash ROM, Zeta SBC V2 compatible memory pager
• Bus: RC2014* compatible
• Microprocessor Supervisor:
  • Reset generation
  • SRAM battery backup
  • Power failure NMI
  • Watchdog

Please refer to Assembly Instructions document

Schematic - Version 1.2

PCB Layout - Version 1.2

Z80-512K uses an Atmel* ATF1504AS CPLD (complex programmable logic device) to implement Zeta SBC V2 compatible memory pager, watchdog control, and UART clock divider. These functions are configured using registers that are accessible using I/O ports. Upon reset, the configuration registers are set to values that result in an RC2014 compatible configuration, so that RomWBW RCZ80_std.rom image can be used without any modifications.

The following I/O ports are implemented in the CPLD:

Bits 0-4 define the ratio the 7.3728 MHz CPU clock (CLK1) is divided by to produce UART clock (CLK2). The output clock can be calculated using the following formula: f_CLK2 (Hz) = 7372800 / (3^m * 2ⁿ), where m is bit 4 of CONFIG register (0 or 1), and n are bits 3-0 of CONFIG register (0 to 15)

• Note: Bits 0-4 are reset to '0' on power-on or reset, so that the divide ratio is set to 1 and the CLK2 frequency is 7.3728 MHz

Bit 5 enables or disables the watchdog and controls the generation of watchdog (WDOG) signal. On the board the WDOG signal is connected to the CPU supervisor IC U5 ADM693A. The CPU supervisor will reset the board if WDOG signal is not pulsed within 1.6 seconds. When watchdog is disabled, the /M1 signal is routed to WDOG signal, so that it is pulsed on every instruction fetch. When watchdog is enabled, the WDOG signal should be pulsed by writting to WDOG register, port 0x6F (see below) in intervals of less than 1.6 seconds.

• Note: Bit 5 is reset to '0' on power-on or reset, so that watchdog is disabled

Any write to this port pulses the WDOG signal, which resets the watchdog in the CPU supervisor U5

• Note: The register is reset to '0' on power-on or reset, which disables the memory paging. When memory paging is disabled the memory page 0 (lower 16 KiB of the Flash ROM) is mapped to all banks.

Connect 3V battery for SRAM backup to this connector.

Important: If the SRAM battery backup is not desired, short J1 with a jumper. Do not leave this connector open.

This connector can be used to program the U4 CPLD

Z80-512K project on Mouser.com - View and order all components except of the PCB.

Z80-512K project on OSH Park - View and order the PCB.

Z80-512K project on Tindie: Complete kit; Z80-512K PCB, a preprogrammed CPLD and optionally a Flash ROM.

Z80-512K uses Atmel ATF1504AS or Intel*/Altera* EPM7064STC44 CPLD (U4) CPLD for memory pager and varous other logic. Atmel CPLD fuse map, Altera CPLD fuse map, and the CPLD source code are provided in CPLD directory of this repository. Use ATMISP software to program Atmel CPLD. Use free Altera Quartus II 13.0sp1 Web Edition to program Altera CPLD. Newer Quartus versions do not support Altera MAX7000 CPLDs.

• Version 1.2

  • Add CPU LED back. Use WDOG signal to control the LED

• Version 1.1

  • Add CPLD STATUS register read back capability
  • Remove LEDs
  • Improve PCB routing: use wider traces where possible, better ground fill
  • Add signal names on the bottom silk screen

• Version 1.0

  • Initial version

• Version 1.1

  • No diagnostic LEDs
    • Workaround: Connect an external LED in series with 1 kohm resistor between U5 pin 11 (WDOG signal) and VCC signal.

• Version 1.0

  • No CPLD STATUS register read back
    • Workaround: Program CPLD with the version 1.1 fuse map. Cut LED_OUT trace at D2 LED (negative terminal), connect U4 pin 36 to U1 pin 21 (RD signal) with a piece of wire. If diagnostic LED is needed, connect negative terminal of the LED to U5 pin 11 (WDOG signal)

• Consider using JST connector for the battery
  • Lower profile than TE latchable connector
  • Ready-made battery holders with JST connectors, such as Adafruit 4191 can be used

Z80-512K is an open source hardware project certified by Open Source Hardware Association, certification UID is US001061. The hardware design itself, including schematic and PCB layout design files are licensed under the strongly-reciprocal variant of CERN Open Hardware Licence version 2. The CPLD VHDL code is licensed under GNU General Public License v3. Documentation, including this file, is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License.

• "RC2014" is a registered trademark of RFC2795 Ltd.
• Other names and brands may be claimed as the property of others.