This code base provides a framework for field-coupled technology-independent open nanocomputing in C++17 using the EPFL Logic Synthesis Libraries. Thereby, fiction focuses on the logic synthesis, placement, routing, clocking, and verification of emerging nanotechnologies. As a promising class of post-CMOS technologies, Field-coupled Nanocomputing (FCN) devices like Quantum-dot Cellular Automata (QCA) in manifold forms (e.g. atomic or molecular), Nanomagnet Logic (NML) devices, Silicon Dangling Bonds (SiDBs), and many more, allow for high computing performance with tremendously low power consumption without the flow of electric current.

With ongoing research in the field, it is unclear, which technology will eventually be competing with CMOS. To be as generic as possible, fiction is able to perform physical design tasks for FCN circuit layouts on data structures that abstract from particular technology or cell design. Using an extensible set of gate libraries, technologies, and cell types, these can easily be compiled down to any desired FCN technology for physical simulation.

The fiction framework is academic software and aims at researchers and developers in the FCN domain who want to obtain cell-accurate circuit layouts from logical specifications or who want to implement their own physical design algorithms.

For these use cases, fiction provides a header-only library that provides data types and algorithms for recurring tasks, e.g., logic network and layout types on different abstraction levels, clocking schemes, gate libraries, placement, routing, clocking, and verification algorithms, etc. Additionally, fiction comes with an ABC-like CLI tool that allows quick access to its core functionality.

Learn more by referring to the full documentation.

If you have any questions, comments, or suggestions, please do not hesitate to get in touch.

For automatic FCN layout obtainment, fiction provides implementations of state-of-the-art physical design algorithms.

Among these are

• SMT-based exact placement and routing
• OGD-based scalable placement and routing
• SAT-based one-pass synthesis

Furthermore, layout correctness can be validated using

• SAT-based formal verification

For logic synthesis, fiction relies on the mockturtle library that offers logic network types and optimization algorithms. Optimized logic networks can then be passed as specifications to physical design algorithms. Alternatively, logic synthesis can be performed in external tools and resulting Verilog/AIGER/BLIF/... files can be parsed by fiction.

Physical design in fiction can be performed technology-independent. Only if resulted layouts are to be physically, simulated, a specific technology implementation is required. To this end, fiction supports various potential FCN implementations together with gate libraries to compile gate-level layout abstractions down to the cell level. Additionally, output formats for state-of-the-art physical simulator engines are supported.

Gate libraries:

• QCA ONE

File formats:

• *.qca for QCADesigner
• *.qll for MagCAD and SCERPA
• *.fqca for QCA-STACK
• *.svg for visual representation

Many thanks to Frank Sill Torres for his support with the QCADesigner format, to Willem Lambooy for his support with the QCA-STACK format, and to Sophia Kuhn for implementing the SVG writer!

Gate libraries:

• ToPoliNano

File formats:

• *.qcc for ToPoliNano
• *.qll for ToPoliNano & MagCAD

Many thanks to Umberto Garlando, Fabrizio Riente, and Giuliana Beretta for their support!

Gate libraries:

• Bestagon

File formats:

• *.sqd for SiQAD

Many thanks to Samuel Sze Hang Ng for his support!

There are highly regular clocking schemes proposed for FCN technologies which can be used as a floor plan for physical design. However, sometimes it can make sense to have more degree of freedom and assign clock numbers on the fly. That is why fiction supports regular and irregular clocking schemes with variable amounts of clock numbers as QCA for instance uses four clock phases but iNML needs only three.

Built-in schemes are

Columnar	Row	2DDWave

USE	RES	ESR

CFE	BANCS

plus the mentioned irregular open clocking that works via a clock map instead of a regular extrapolated cutout.

With many FCN technologies considered planar, wire crossings should be minimized if possible. However, there are some options in QCA where, using a second layer, crossings over short distances and co-planar rotated cells become possible. As both are just technical implementations of the same concept, fiction supports crossings as wires in a second grid layer in its data structures. They will also be represented as such in corresponding SVG and QCADesigner output. However, note that it is to be interpreted as the concept of crossings and could also be realized co-planar.

Wires are only allowed to cross other wires! Wires crossing gates is considered to lead to unstable signals.

In the literature, both is seen: having input cells (pins) directly located in the gate structure or using designated I/O elements which are located outside of gates. This distinction only makes sense on the gate-level and fiction supports both approaches and offers usage in the implemented physical design algorithms.

Gate-level abstraction has its limits. Often, chip area is wasted when only using a single wire per tile. In fiction, cell-level layouts allow for precise control over cell placement and can, thus, also create multiple wire segments per clock zone. Physical simulation can give an indication whether the built structures are implementing the intended functionality.

A technology extension proposes to utilize the external clock signal generator in an unconventional way: by creating further asymmetric clock signals with extended Hold phases that are assigned to specific wire tiles, synchronization elements can be created that stall signals over multiple clock cycles. These artificial latches are able to feed information to any other clock number, but their usage reduces the overall throughput of the layout. In return, long wire detours for signal synchronization can be prevented.

Designed layouts can be evaluated with regard to several cost functions. The following metrics are currently implemented:

Gate-level layouts:

• Circuit dimension in tiles
• Number of gate tiles
• Number of wire tiles
• Number of wire crossings
• Number of synchronization elements
• Critical path
• Throughput
• Bounding box
• Energy dissipation based on a physical model (QCA only)

Cell-level layouts:

• Circuit dimension in cells
• Number of cells
• Bounding box
• Area usage in nm²