bmpenuelas / systemverilog-formatter-vscode Goto Github PK

Since the extension doesn't have default keybinds, I experimented and used these keyboard shortcuts. These mimic the same functionality that vscode provides for supported languages.

For supported languages, ctrl + k, ctrl + f autoformats the selection
For supported languages, alt + shift + f autoformats the entire document

[
    {
        "key": "ctrl+k ctrl+f",
        "command": "systemverilog-formatter-vscode.formatSelection",
        "when": "editorTextFocus && !editorReadonly && resourceExtname == '.sv'"
    },
    {
        "key": "shift+alt+f",
        "command": "systemverilog-formatter-vscode.formatDocument",
        "when": "editorTextFocus && !editorHasDocumentFormattingProvider && !editorReadonly && resourceExtname == '.sv'"
    }
]

I added a check so that it only works for .sv filetypes only (will not interfere with other filetypes or other shortcuts). I tried to find a way to add this within the extension's source code, but I haven't spent enough time with it to figure it out.

Hopefully this can be implemented in the next update!

verible now have windows builds
https://github.com/chipsalliance/verible/releases

By default, the formatting of various code snippets is automatically inferred from existing code, which is not in line with my usage habits. I hope that all port declarations, assignments, etc. in the code can be aligned.

After I install this plugin, the format function always intermittent work,I can't figure it out what's the problem with it

Hi,bmpenuelas.
Thanks for your work!
It works very good in systemverilog. But I also need a verilog formatter as well.
I think Verible also handle verilog file as well. Can you add that as well?
Thanks!

I believe the issue is with the file path not being parsed correctly (since my username has a space in it). The command works fine if I execute it myself in the command line.

"CentOS-7" is missing as possible option

I notice this doesn't officially support MACOS (only for now, I wish)...BUT I really need to it so I decided to give it a try anyway.
I use brew to install verible, and I can get the "verible-verilog-format" run in the terminal.
So I try to use 2.16.3 with {"systemverilogFormatter.veribleBuild": "none"} in the setting SJON. The log I got is

#命令"SystemVerilog Formatter - Format this file"导致错误 (Command failed: -
/bin/sh: -: command not found
)

After roll back to 2.16.2 everything seems to work just fine.......

I have Verible binaries in the PATH and they are accessible in my BASH terminal. VS Code is trying to run Verible with /bin/sh even though BASH is set in VS Code terminal.integrated.shell.linux

2023-06-07 12:16:02.708 [error] [bmpenuelas.systemverilog-formatter-vscode] provider FAILED
2023-06-07 12:16:02.708 [error] Error: Command failed: verible-verilog-format -
/bin/sh: verible-verilog-format: command not found

Could you please help me with this issue?

我在一个新机器上安装这个插件，是安装在vscode远程宿主机上的，发现一运行就报这个错误不知道是为什么
单独下载verible 使用verible-verilog-format是正常的。
SystemVerilog: Indexing: Unable to process file: file:///data/mxwang/Project/FPGA/ZCU104/wpu_acc_mig_base/wpu_acc_mig_base.srcs/sim_1/imports/new/tb_axi_mig_wrapper.sv TypeError: Cannot read properties of undefined (reading 'body') Auto Indexing: file:///data/mxwang/Project/FPGA/ZCU104/wpu_acc_mig_base/wpu_acc_mig_base.srcs/sim_1/imports/new/tb_axi_mig_wrapper.sv SystemVerilog: Indexing: Unable to process file: file:///data/mxwang/Project/FPGA/ZCU104/wpu_acc_mig_base/wpu_acc_mig_base.srcs/sim_1/imports/new/tb_axi_mig_wrapper.sv TypeError: Cannot read properties of undefined (reading 'body') Auto Indexing: file:///data/mxwang/Project/FPGA/ZCU104/wpu_acc_mig_base/wpu_acc_mig_base.srcs/sim_1/imports/new/tb_axi_mig_wrapper.sv SystemVerilog: Indexing: Unable to process file: file:///data/mxwang/Project/FPGA/ZCU104/wpu_acc_mig_base/wpu_acc_mig_base.srcs/sim_1/imports/new/tb_axi_mig_wrapper.sv TypeError: Cannot read properties of undefined (reading 'body') Auto Indexing: file:///data/mxwang/Project/FPGA/ZCU104/wpu_acc_mig_base/wpu_acc_mig_base.srcs/sim_1/imports/new/tb_axi_mig_wrapper.sv SystemVerilog: Indexing: Unable to process file: file:///data/mxwang/Project/FPGA/ZCU104/wpu_acc_mig_base/wpu_acc_mig_base.srcs/sim_1/imports/new/tb_axi_mig_wrapper.sv TypeError: Cannot read properties of undefined (reading 'body')