black-parrot-hdk / zynq-parrot Goto Github PK

Hi,
I was doing the make prep command and it failed at this part showing makefile error related to patches is there any solution to this ,running on Ubuntu 22.04.4 LTS

make gnudramfs_build
make[3]: Entering directory '/home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk'
cat: /etc/centos-release: No such file or directory
#cd /home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk/riscv-gnu-toolchain; git apply --ignore-whitespace --ignore-space-change /home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk/patches/riscv-gnu-toolchain/.patch
cd /home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk/riscv-gnu-toolchain; git apply --ignore-space-change --ignore-whitespace /home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk/patches/riscv-gnu-toolchain/.patch
error: patch failed: .gitmodules:13
error: .gitmodules: patch does not apply
make[3]: *** [/home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk/Makefile.tools:36: gnudramfs_build] Error 1
make[3]: Leaving directory '/home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk'
make[2]: *** [/home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk/Makefile.tools:80: /home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk/install/touchfiles/tools/gnudramfs.ae9efcc33c4968f97ab89b4b13c7f6520b145f94] Error 2
make[2]: Leaving directory '/home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk'
make[1]: *** [Makefile:42: sdk_lite] Error 2
make[1]: Leaving directory '/home/vboxuser/Desktop/zynq-parrot/software/import/black-parrot-sdk'
make: *** [Makefile:12: prep] Error 2

BlackParrot should not block on these FIFOs, instead the counters should be checked, and if an attempt to a read an empty or write a full fifo should complete in AXI-land without stalling. This is how we separate the two systems and prevent deadlock. In particular, restrictions inside BP about only handling one transaction at a time mean that we could have PS waiting on PL/BP and PL/BP waiting on PS.

I am not sure if we can get race condition in the signal "this->p_awready" in the following line:

In line 180 we set "this->p_awvalid" to 1 and check if "this->p_awready" is high to see if the handshaking will happen. However, if p_awready is actually a YUMI signal that depends on awvalid, is it possible that awready would be read and written at the same time slot?

For example, let's assume that in some time slot, "this->p_awready" will be high if "this->p_awvalid" is set to 1. Now if the simulator reads "this->p_awready" and gets 0 instead of 1 at line 202, the simulation will fail as the code in bsg_axil will think that the handshaking will not happen but actually it will.

add35a1

I get weird dump values even after the hello world prog.nbf runs successfully with VCS:

This is part of the nbf loading process. s01 carries the nbf data and you can see 's01_axi_awaddr' has 'X', 'Z' even when the corresponding valid bit is high.

To keep certain members of the group happy. We should replace the static axil members with a singleton containing pointers to them

On master branch (hash: 877fb71 link),
the 'state_n' variable will become latches due to incomplete case.

Also note that in bp_me_axil_client in the imported black-parrot repo, 'state_n' has similar issue. bp_me_axil_master does not have this problem though. I have already filed a separate issue about this on black parrot repo.

Commit I'm using: 556d15c

In the BP example, normally no matter how slow the PS reads the BP outputs from PL, the data should still be complete without missing/corrupting. However if we write a simple program like the following:

int main()
{
    for(;;) {
        printf("Hello how are you doing?\n");
    }
    return 0;
}

... and modify the following function in ps.cpp to simulate the slow polling in PS:

void *device_poll(void *vargp) {
  bp_zynq_pl *zpl = (bp_zynq_pl *)vargp;
  unsigned select = 0;
  while (1) {
#ifndef FPGA
    zpl->axil_poll();
#endif

    if((select++ % 128) == 0) {
      // keep reading as long as there is data
      if (zpl->axil_read(GP0_RD_PL2PS_FIFO_CTRS + gp0_addr_base) != 0) {
        decode_bp_output(zpl, zpl->axil_read(GP0_RD_PL2PS_FIFO_DATA + gp0_addr_base));
      }   
    } else {
        zpl->axil_read(GP0_RD_CSR_RESET + gp0_addr_base);
    }   

    // break loop when all cores done
    if (done_vec.all()) {
      break;
    }   
  }
  bsg_pr_info("Exiting from pthread\n");

  return NULL;
}

Then the output got by PS will be corrupted/missing.

After looking at the waveform, the problem could be from BP instead of the AXI bus, as the strange data do actually come out from BP unicore.

I have also seen cases where PS also gets missing output from BP in simulation even if we do not simulate the slow PS polling like with the above code, but currently I do not have test cases that can reproduce that.

I was trying to build the repo in a different computer and can't avoid this error, I already tried deleting all files, clone, checkout and prep again, however this missing file error persists. Could it be a problem with my build?

I also tried going to zynq-parrot/cosim/import/black-parrot-tools/ and

make bleach_all

then

make prep

again, however this error always shows up:

make -C /home/teo/zynq-parrot/cosim/import/black-parrot-tools/yosys
make[4]: Entering directory '/home/teo/zynq-parrot/cosim/import/black-parrot-tools/yosys'
[  0%] Building kernel/version_8f07a0d84.cc
[  0%] Building kernel/version_8f07a0d84.o
gcc: **fatal error**: cannot execute ‘cc1plus’: execvp: No such file or directory
compilation terminated.
make[4]: *** [Makefile:762: kernel/version_8f07a0d84.o] Error 1

The master branch I'm looking at: hash: 877fb71.

Problem Description:

The synthesis process went well and I was able to get bitstream without any critical warnings/errors from vivado, but when I loaded into the PL and then ran the ps.cpp program, the OS seemed to be completely stuck. The above description applies to both Zedboard and PYNQ Z2. Please see the attached screenshot for this tragedy:

I'm now actively looking at this and will do updates here as soon as I make any progress.

Hi，I want to run hammerblade-example, BP with bsg_manycore mesh accelerator.
I want to know the exact minimal zynq fpga model needed and I'm worried the resources may not be enough.
Thanks.

https://docs.google.com/document/d/1mBLb9BgQSIv25p59MPj0a4c-TfvwlfqXeuFlZFBVzAY/edit#

On a Centos 7 install with Vivado 2019.2, there are various errors. This is a tracking issue, will post more details as available

So continue with my debug adventure -- I am still using add35a1.

Now I can run opensbi v1.0 + Linux kernel 5.15 on FPGA, but then I find I cannot launch ps.cpp more than once if I do not re-loading the bitstream. Not quite sure if this is something we expect.

I guess it is because when we re-run ps.cpp, only the reset for BP gets triggered. Other resets like for AXIs are only triggered during the bitstream loading.

From the below screenshot, we can see the first run on the top went well, but the second run below got stuck.

Building the SDK in zynq-parrot implicitly causes the zynq-parrot platform to be set. We should document this and migrate targets from zynq-parrot repo to SDK

See:

Looks like this results in some warnings being thrown, but don't know if there are worse consequences. Should be cleaned up.

Hello, I am trying to build the black-parrot-example, for my research project of applying DFX in multicore RISC-V processors, since my lab has a ZCU-104 I tought this would be a great starting point, however I have problems in building any of the files under cosim directory, the same warnings always happens. I will show the errors and my attempt to fix them. I am running vivado 2022.1 and Ubuntu 22.04

during fpga_build_ip:

WARNING: [IP_Flow 19-4656] Synthesis file group is packaged with a Dependency property value '/home/teo/bp-hdk/zynq-parrot/cosim/shell-example/v' although it may not be recognized as a synthesis -include_dir property after IP delivery.

WARNING: [IP_Flow 19-4656] Synthesis file group is packaged with a Dependency property value '/home/teo/bp-hdk/zynq-parrot/cosim/import/basejump_stl/bsg_misc' although it may not be recognized as a synthesis -include_dir property after IP delivery.

WARNING: [IP_Flow 19-4656] Synthesis file group is packaged with a Dependency property value '/home/teo/bp-hdk/zynq-parrot/cosim/import/basejump_stl/bsg_test' although it may not be recognized as a synthesis -include_dir property after IP delivery.

WARNING: [IP_Flow 19-4656] Synthesis file group is packaged with a Dependency property value '/home/teo/bp-hdk/zynq-parrot/cosim/include/vivado' although it may not be recognized as a synthesis -include_dir property after IP delivery.

WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/teo/bp-hdk/zynq-parrot/cosim/import/basejump_stl/bsg_test/bsg_nonsynth_dpi_clock_gen.cpp'.

WARNING: [IP_Flow 19-5101] Packaging a component with a SystemVerilog top file is not fully supported. Please refer to UG1118 'Creating and Packaging Custom IP'.

Here I open the gui and all these files show up as being part of the project and enabled, so I really don't understand what is wrong, but I do belive that this is generating the errors for the next step.

during fpga_build_block:

CRITICAL WARNING: [filemgmt 20-730] Could not find a top module in the fileset sources_1.
Resolution: With the gui up, review the source files in the Sources window. Use Add Sources to add any needed sources. If the files are disabled, enable them. You can also select the file and choose Set Used In from the pop-up menu. Review if they are being used at the proper points of the flow.


WARNING: [xilinx.com:ip:smartconnect:1.0-1] shell_bd_1_smartconnect_0_0: IP shell_bd_1_smartconnect_0_0 is configured in Low-area mode as all propagated traffic is low-bandwidth (AXI4LITE). SI S00_AXI has property HAS_BURST == 1. WRAP bursts are not supported in Low-area mode and will result in DECERR if received.

WARNING: [xilinx.com:ip:smartconnect:1.0-1] shell_bd_1_smartconnect_0_0: If WRAP transactions are required then turn off Low-area mode using ADVANCED_PROPERTIES. Execute following: set_property CONFIG.ADVANCED_PROPERTIES {__experimental_features__ {disable_low_area_mode 1}} [get_bd_cells /shell_bd_1_smartconnect_0_0]

WARNING: [BD 41-927] Following properties on pin /top_0/aclk have been updated from connected ip, but BD cell '/top_0' does not accept parameter changes, so they may not be synchronized with cell properties:
	FREQ_HZ = 177777771 
Please resolve any mismatches by directly setting properties on BD cell </top_0> to completely resolve these warnings.

This warnings end up generating errors and stop the building process. For the top module I tried opening the gui, and searching for the file defined as top, and that file is exactly top.v, which is enabled.

Unfortunately I do not have much time to spare and look more thoroughly through the entire project structure so if I could get some directions where to look it would really help.