ben-marshall / uart Goto Github PK

Hej Ben!
I am a student currently writing my final thesis. I write some HDL designs for the Xilinx Ultrascale for that and therefore searched a UART lib under MIT licence and found yours, thanks for sharing :)

I had 2 minor issues and one convenience hick up after checking out the repo when doing make rx tx.
My setup is MANJARO with kernel 5.10.41 and icarus verilog version 11.0
My issues where:

• no work dir present (the convenience thing), I like to keep build folders around with a empty .keep file, that you can build without the error-mkdir-rebuild loop if you agree on the convenience of that ^^
• the clock assignment in the tx_tb didn't work ootb for me, when I changed the statement (see diff) the next error appeared =>
• test_uart_tx.v:86: error: Unable to bind wire/reg/memory 'i_uart_tx.SAMPLES_THRESHOLD' in 'tb', I thing you maybe deleted that parameter from the actual design?!

After these two essential changes I could run the tb-sim succesfully :)
Maybe I did not get anything or overlooked something (I only did some small verilog/icarus stuff for little homework projects before, so mercy on my naitivity ;))

Thanks again for sharing your UART modules!
Greetings!

Lots of bytes string int conversions were removed in python3 which breaks the comms.py test script

I used this uart reciever andwith arty 35 and after synthesis the LUT count is 25 instead of 51 and simulation are failing post synthesis.

Hello.
I'm interested in your uart implementation and I want to use your uart repos for my studies and projects.
So, I want know this repo's license please.