In this project, I implemented a 32-bit pipelined microarchitecture RISC-V processor based on Harvard Architecture with full hazard handling. In the pipelined microarchitecture, I design it by subdividing the single-cycle processor into five pipeline stages. Thus, five instructions can execute simultaneously, one in each stage. In other words, instruction fetch, instruction decode, execute, write back, and program counter update occurs within a single clock cycle.Because each stage has only one-fifth of the entire logic, the clock frequency is approximately five times faster. So, ideally, the latency of each instruction is unchanged, but the throughput is five times better.

The Hazard Unit computes control signals for the forwarding multiplexers to choose operands from the register file or from the results in the Memory or Writeback stage (ALUResultM or ResultW). The Hazard Unit should forward from a stage if that stage will write a destination register and the destination register matches the source register. However, x0 is hardwired to 0 and should never be forwarded. If both the Memory and Writeback stages contain matching destination registers, then the Memory stage should have priority because it contains the more recently executed instruction. In summary, the function of the forwarding logic for SrcAE (ForwardAE) is given on the next page. The forwarding logic for SrcBE (ForwardBE) is identical except that it checks Rs2E instead of Rs1E Complete single-cycle RISC-V processor. implementation.

Pipelined processor with full hazard handling

in this Project, I ran three projects to test it: 1st program: simple counter program counts from 0 to 255. 2nd program: the Fibonacci series numbers. 3rd program: the factorial of 8.

simulation result of 1st program(simple program counter)

simulation result of 2nd program(the Fibonacci series numbers)

simulation result of 3rd program(the factorial of 8)

top level view using Quartus Prime Lite Edition