awmiller / arm-cpu-core Goto Github PK

What steps will reproduce the problem?
1. write small program which contains next instructions in specified order:
    MOV r0,#0xa50000
    LDR r0,=0x123456
    STM r1,{r0,r2}
2. compile
3. run

What is the expected output? What do you see instead?
Expected output is writing value 0x123456 and then value of R2 to memory 
starting from R1. But actual result is write of 0xa50000 and then value of R2.

I cannot find the verilog source file for this project. How can I get it?

What steps will reproduce the problem?
1. create small program with vector table, primitive FIQ/IRQ handlers (subs 
pc,lr,#4) and ldr r3,=label;ldm r3,{r3,r4} in main(), compile and execute in 
simulator.
2. generate one clock IRQ or FIQ when cpu executes ldm instruction (at same 
time as ram_cen raises)
3. step until CPU returns from exception handler.

What is the expected output? What do you see instead?
CPU should finish LDM instruction, branch to handler and return to next 
instruction after LDM. But LDM is interrupted in middle of his job (it loads 
only first register then ram_cen lowered and second keeps unchanged), handler 
returns to LDM instruction and tries to execute it again. But base register is 
corrupted. So execution repeat does wrong result or may cause data abort.

What version of the product are you using? On what operating system?
CPU is taken from linux.rar package.

Please provide any additional information below.

I think it can be fixed by ANDing rom_en and fiq/irq signals.