SytemVerilog implementation of Alpha-Data CNN example originally in VHDL
The original VHDL and whitepaper can be found here: ftp://ftp.alpha-data.com/pub/appnotes/cnn/
SystemVerilog Simulator: Commercial (free): altera modelsim or Vivado simulator Commercial (non-free): VCS, Questa, Modelsim, Aldec, Incisive(?) Free: verilator (requires System-C testbench, not currently implemented or tested)
FPGA (Eventually): Xilinx SOC: Zynq, Zynq Ultrascale+ (preferred) Altera SOC
Software side: TBD
TBD
TBD
Add additional notes about how to deploy this on a live system
TBD
- Alpha-Data for the original CNN library in VHDL
- Frank Bruno for SystemVerilog implementation
See also the list of contributors who participated in this project.
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- Alpha Data for the original implementation and allowing me to do this port.