It seems that the extension parses the include globs and expects the paths provided in the include globs to be inside the workspace always. This is not necessarily the case in projects where we refer to external IPs.

Environment

• OS:

NAME="Rocky Linux"
VERSION="8.9 (Green Obsidian)"
ID="rocky"
ID_LIKE="rhel centos fedora"
VERSION_ID="8.9"
PLATFORM_ID="platform:el8"
PRETTY_NAME="Rocky Linux 8.9 (Green Obsidian)"
ANSI_COLOR="0;32"
LOGO="fedora-logo-icon"
CPE_NAME="cpe:/o:rocky:rocky:8:GA"
HOME_URL="https://rockylinux.org/"
BUG_REPORT_URL="https://bugs.rockylinux.org/"
SUPPORT_END="2029-05-31"
ROCKY_SUPPORT_PRODUCT="Rocky-Linux-8"
ROCKY_SUPPORT_PRODUCT_VERSION="8.9"
REDHAT_SUPPORT_PRODUCT="Rocky Linux"
REDHAT_SUPPORT_PRODUCT_VERSION="8.9"

• config: { "verilog.ctags.indexAllIncludes": true, "verilog.excludeGlob": "**/work/*", "verilog.lint.slang.path": "slang", "verilog.lint.slang.args": "--error-limit 200", "verilog.svFormat.verible.path": "verible-verilog-format", "verilog.ctags.path": "ctags", "verilog.includeGlobs": [ "/path/to/uvm-1.2/*.{sv,svh}", ], }

Steps to reproduce:

• Open Workspace
• Run re-index step-

Logs: (Get logs from Output > verilog)

2024-06-12 09:51:40.162 [info] [ctags] indexing 0 .svh files
2024-06-12 09:51:40.162 [info] [ctags] indexed 0 .svh files
2024-06-12 09:51:40.162 [info] ctags index includes finished
2024-06-12 09:51:40.190 [info] [index] indexing 18 files
2024-06-12 09:51:40.190 [info] index files finished

Describe the bug
When the variable type is declared in the module declaration port list, the last port name is not colored correctly, the name is the same color as the port type.

Environment (please complete the following information):

• OS: Windows 11 pro 23h2

• vscode:
  Version: 1.89.1 (user setup)
  Commit: dc96b837cf6bb4af9cd736aa3af08cf8279f7685
  Date: 2024-05-07T05:13:33.891Z
  Electron: 28.2.8
  ElectronBuildId: 27744544
  Chromium: 120.0.6099.291
  Node.js: 18.18.2
  V8: 12.0.267.19-electron.0
  OS: Windows_NT x64 10.0.22631

• vscode-system-verilog
  v0.9.10

Steps to reproduce
Steps to reproduce the behavior:

1. create module declaration
2. terminate last port line with newline

output fsk_sym_o,
output fsk_sym_n_o
);

if the ");" is moved to the end of the port line "output fsk_sym_n_o);" the problem does not occur.

Log
Attach the log generated while following the above steps

Expected behavior
port type and name should have different color.

Actual behavior
port name is same as port type

Additional context
Add any other context about the problem here.

Environment

• OS:

Operating System: Rocky Linux 9.4 (Blue Onyx)       
Kernel: Linux 5.14.0-427.28.1.el9_4.x86_64

• config:

   "verilog.ctags.path": "/usr/local/bin/ctags",
   "verilog.ctags.indexAllIncludes": true,
   "verilog.svFormat.formatter": "verible-verilog-format",
   "verilog.verilogFormat.formatter": "verible-verilog-format",
   "verilog.svFormat.verible.path": "/opt/verible/bin/verible-verilog-format",
   "verilog.verilogFormat.veribleFormatter.path": "/opt/verible/bin/verible-verilog-format"

Steps to reproduce:

• Right clock in document, select Format Document

Logs: (Get logs from Output > verilog)

2024-08-14 15:11:29.047 [info] [svFormat] formatting /home/gtaylor/git/fpga/src/clock_crossing/two_stage_synchronizer.sv
2024-08-14 15:11:29.047 [info] [svFormat] [verible] Temp file created at:/tmp/verible-verilog-format-c04d7d624381cefe245a29da3e69dfad.tmp.sv
2024-08-14 15:11:29.047 [info] [svFormat] [verible] Executing command: /opt/verible/bin/verible-verilog-format  --inplace /tmp/verible-verilog-format-c04d7d624381cefe245a29da3e69dfad.tmp.sv
2024-08-14 15:11:29.048 [error] [svFormat] [verible] Error: Command failed: /opt/verible/bin/verible-verilog-format  --inplace /tmp/verible-verilog-format-c04d7d624381cefe245a29da3e69dfad.tmp.sv
<empty-filename>: No such file or directory

It appears ctags has an option to index .svh files, but this option is lacking for slang. Imports from .svh are highlighted as errors by slang (the error goes away if the imported file is renamed to .sv).

Describe the bug
When the extension calls iverilog to lint the code an error

"C:\iverilog\bin\iverilog.exe" not found. Configure verilog.lint.iverilog.path, add to PATH, or disable in config.

The log output shows that the path is not the problem with the linter. The extension finds the iverilog.exe fine. The error reported by iverilog is that it can't find the null.conf file

Steps to reproduce

1. Install iverilog
2. Enable iverilog as a linter in settings

Log
2024-05-19 14:17:36.642 [info] [lint] [iverilog] linting file:///s%3A/GitRepo/xxx.v

2024-05-19 14:17:36.642 [info] [lint] [iverilog] Running $s:\GitRepo\xxx:
C:\iverilog\bin\iverilog.exe -t null -g2005 -Is:/GitRepo/xxx s:/GitRepo/xxx.v

2024-05-19 14:17:36.700 [error] [lint] [iverilog] Error: Command failed: C:\iverilog\bin\iverilog.exe -t null -g2005 -Is:/GitRepo/xxx s:/GitRepo/xxx.v

ERROR: Unable to read config file: C:\iverilog\lib\ivl\ null.conf

Expected behavior
vscode highlights errors in code

Actual behavior
No highlights, error is reported stating that the iverilog.exe executable can not be found.

Additional context
The iverilog.exe is in my path, and the error occurs even when the full path is configured in extension settings.

The extension badge is not showing on Linux for me:

It's not hidden:

On Windows it's ok. Only on Linux this happens. Do you think it could be an issue in the extension?

Environment

• VS Code version: 1.83.1
• Commit: f1b07bd25dfad64b0167beb15359ae573aecd2cc
• Date: 2023-10-10T23:45:31.402Z
• Electron: 25.8.4
• ElectronBuildId: 24154031
• Chromium: 114.0.5735.289
• Node.js: 18.15.0
• V8: 11.4.183.29-electron.0
• OS: Linux x64 3.10.0-1160.92.1.el7.x86_64 (CentOS Linux release 7.9.2009 (Core))
• Config: no json config edited for this extension; I'm using slang-6.0 and uctags-2024.06.20-linux-x86_64 added to Linux PATH

Logs:

2024-07-31 13:33:14.726 [info] [index] index activating
2024-07-31 13:33:14.726 [info] [ctags] activating
2024-07-31 13:33:14.726 [info] [lint] activating lint manager
2024-07-31 13:33:14.726 [info] [lint] [slang] linter config updated
2024-07-31 13:33:14.726 [info] [lint] [modelsim] linter config updated
2024-07-31 13:33:14.726 [info] [lint] [iverilog] linter config updated
2024-07-31 13:33:14.726 [info] [lint] [verilator] linter config updated
2024-07-31 13:33:14.726 [info] [lint] [xvlog] linter config updated
2024-07-31 13:33:14.726 [warning] [lint] skipping lint for non verilog file
2024-07-31 13:33:15.357 [info] [ctags] indexing 0 .svh files
2024-07-31 13:33:15.358 [info] [ctags] indexed 0 .svh files
2024-07-31 13:33:15.358 [info] index files finished
2024-07-31 13:33:15.358 [info] AndrewNolte.vscode-system-verilog activation finished.
2024-07-31 13:33:15.358 [info] ctags index includes finished
2024-07-31 13:33:26.354 [warning] [lint] skipping lint for non verilog file

It would be nice if the extension was published on Open VSX to make installation easier in VS Code compatible editors :)

Thanks!

Describe the bug - A clear and concise description of what the bug is.

There appears to be a problem with the way this extension works with the vscode config parser.
In that, unlike other extensions, it is storing the settings as quoted text representing YAML, rather than YAML itself.

Settings for paths that are altered from default look like this on disk:

"verilog.ctags.path": "{\"windows\":\"ctags.exe\",\"linux\":\"~/.local/bin/ctags\",\"mac\":\"ctags\"}",

Whereas they should look like this:

"verilog.ctags.path": {"windows":"ctags.exe","linux":"~/.local/bin/ctags","mac":"ctags"},

In the above, note the escaped quotes \"....\" and quoted value string "{....}" in the first example. If changed to the canonical form in the 2nd example the settings editor throws an error. Note: The rest of the relevant extenion settings are attached below.

Perhaps the schema for the config entries is incorrect? It wants string and it should be a yaml structure. As it is a string (containing a line of yaml text) could it be being misinterpreted as a path, causing the error seen in this issue?

I also think this is true for all the extension settings that require a path and not just ctags I am reporting here. Though I don't have most of them so can't be sure

Other related issues (I can split these out as separate related issues as required):

I am guessing here, likely because of this incorrect parsing it is not seeing the POSIX shell tilde ~, usually meaning ${HOME} or similar.
If that is not the case then this should be reviewed as this works with other paths in vscode. This is essential as remote systems don't always have absolute global paths or guarantee passing environment variables when projects are shared between multiple users.

Root cause - vague setting names?

Perhaps the root cause is that the settings dialog is inconsistent with the use of path as this is unclear if this means executable path, tool location or executable filename path. I would suggest making this clearer by renaming the dialog prompt and setting keys consistently, such that 'path' accepts either a prefix or a full filename path. And where it must and can only be a path, use something like tool_path_prefix, as that settings only accepts a path as it points to more than one file. Pointing it to a file should be an error, though I don't know if the schema checker can express that? Having one setting that means both prefix and name could be a problem or cause odd things to happen. Perhaps just separate it as shown below.

Specifically:
Conforming to the way similar standard vscode settings work, when providing a path it should resolve to YAML the value of which accepts an optional platform qualifier, e.g. string
"ctags_executable": "ctags"

or - per platform using a key-value pair
"ctags_executable": {"linux": "ctags"}

And (again following conventions) similar settings where appropriate, this should accept empty "", meaning a built-in implicit 'standard' filename (in this case "ctags") with an optional user overriding file name, a user prefix path to the standard name or an explicit full path to an executable, e.g. Alternate executable
"ctags_executable": "myctags"

or - implied "ctags" executable
"ctags_executable": "~/path/to/localbuilds"

or - explicit "myctags" executable
"ctags_executable": "~/local/bin/myctags"

Extension settings (and logging/extension host) prefix.

The YAML key verilog.ctags.path is being set globally, through the name 'verilog', therefore it conflicts with other similar extensions if they also start with "verilog......". This is true of the extension host too. Perhaps change 'verilog' to the name of this repo, andrewnolte.vscode-system-verilog or something similar, so that settings are within a container specific to this extension. Now the above examples would look something like this:

"andrewnolte.vscode-system-verilog": {
  "ctags.path": "ctags",
  "ctags.executable: "",
  ....
}

Environment:

• Linux Ubuntu 22.04 (remote)
• Win11 Host, latest VSCode
• config: see code block below

{
    "verilog.ctags.indexAllIncludes": true,
    "verilog.lint.slang.enabled": true,
    "verilog.ctags.path": "{\"windows\":\"ctags.exe\",\"linux\":\"~/.local/bin/ctags\",\"mac\":\"ctags\"}",
    "verible.path": "~/.local/bin",
    "verilog.languageServer.veribleVerilogLs.path": "~/.local/bin/verible-verilog-ls",
    "verilog.languageServer.veribleVerilogLs.enabled": true,
    "verilog.verilogStandard": "Verilog-2005",
    "verilog.lint.slang.path": "{\"windows\":\"slang.exe\",\"linux\":\"~/.local/bin/slang\",\"mac\":\"slang\"}",
    "verilog.lint.verilator.enabled": true,
    "verilog.svFormat.verible.path": "{\"windows\":\"verible-verilog-format.exe\",\"linux\":\"~/.local/bin/verible-verilog-format\",\"mac\":\"verible-verilog-format\"}",
    "verilog.svStandard": "SystemVerilog-2017"
}

Steps to reproduce:

• change the setting for ctags on remote workspace
  I have no idea if this issue is only on a remote or if the same is true for local and/or workspace settings.

Logs: (Get logs from Output > verilog)

There is little or nothing to add from the system log or the extension log. I can send this if required but it has to be sanitised due to corporate rules about sharing internal information.

I get these popup dialogs, repeated every time a HDL file goes into scope.

X
"" not found. Configure verilog.ctags.path, add to PATH, or disable in config.

Source: Verilog/SystemVerilog Tools