andre-richter / pcie-lat Goto Github PK

The code was not working for my server, running on Ubuntu 14.04 server. Please include the vmalloc file.

Another issue I faced was the number and graph explanation. It would be nice if you could add some explanation so that people can interpret the numbers/graph easily.

Thanks,
Ankit

Thanks for sharing your tool .
wanna check if any plan with ARM64 support or could advice on it, would be appreciated!

Hi Andre,
I am using 2 x86 Intel CPUs and one microsemi PCIe switch between them. Ubuntu 18.04 is running on both CPUs. I am sure that the PCIe-switch is right configured and PCIe driver on both CPU are also correct. But I got the following results which is very strange. Do you have some ideas about that? Thx!

TSC freq: 2095077000.0 Hz
TSC overhead: 32 cycles
Device: b3:00.1
BAR: 0
Offset: 0x0
Loops: 100000

   | Results (100000 samples)

Mean | 32612.38 cycles | 15566.20 ns
Stdd | 47215.27 cycles | 22536.29 ns

   | 3σ Results (92867 samples, 0.071% discarded)

Mean | 19535.33 cycles | 9324.40 ns
Stdd | 1600.78 cycles | 764.07 ns

Hi Andre,
I'm using pcie-lat to measure my pcie device latency.
And i'm understand that pcie-lat measure reading of configuration space register time.
Is there any method to measure data register access time or device-memory access time?

On a server I'm running this utility on, I encounter unreasonable clock frequencies.

For example:

TSC freq:     1034704.0 Hz
TSC overhead: 27 cycles

The clock frequency is actually 5GHz. This yields unlikely PCIe latency results, like:

       | Results (1000 samples)
------------------------------------------------------
Mean   |  11218.96 cycles | 10842679.65 ns
Stdd   |    390.80 cycles | 377693.83 ns