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I am looking for assistance in designing a PCBA that is compatible with the Stargazer Backplane, a 40 pin, 0.1" header.

Design notes:

• It should be roughly equivalent to the Feather Template used for the Stargazer
• A low profile socket for the Adafruit Feather footprint
• Some kind of way of gating the SPI lines based on the GO signal, similarly to the SN74AC245N used in the CPU card
• It should have some kind of jumper, switch, or solder bridge to select which GO signal it listens to
• Optional: It would be nice to have a low profile Featherwing socket as well
• By default, the "MISO", "MOSI" ("CIPO" and "COPI") and "SCK" lines from the feather footprint should be used for the SPI connections.
• Connection from the Bus 3.3v pin and the Feather 3.3v pin should be jumpered or solder bridged (in case 5v power is used)
• There should be a weak (10k?) pullup on the OE/GO line
• If using an SN74AC245N, unused INPUT pins should be pulled in a consistent direction
• Pin headers should be provided for SWD lines, as these will probably require fly-wires from the feather itself
• Pins not used for the Anachro connections should have some kind of header available for use

Edit:

I wanted to add a couple notes.

1. I'd like to be able to order these boards relatively cheaply through a service like JLCPCB or OshPark
2. I'd like these boards to be mostly through-hole compatible, so that they are easily solderable as kits, OR to be orderable fully populated (e.g. with JLCPCB's assembly service)
3. I am willing to fund the first couple hardware spins (PCBs, Components) for this. Please get confirmation from me directly BEFORE ORDERING if you would like me to pay for this or reimburse you.

I am looking for assistance in designing a PCBA that is compatible with the Stargazer Backplane, a 40 pin, 0.1" header.

Design notes:

• It should be roughly equivalent to the Arbitrator V1 card used for the Stargazer
• A low profile socket for the Adafruit Feather footprint
• Connection from the Bus 3.3v pin and the Feather 3.3v pin should be jumpered or solder bridged (in case 5v power is used)
• Pins not used for the Anachro connections should have some kind of header available for use

Open Questions:

• What pins most commonly expose SPI Peripheral functionality on feathers? On the nRF52, any pin can be configured, but not all boards are like this. Do we just need to have some kind of solder bridge/jumpers available so people can connect their own pins?
• I would like some kind of connection suitable for QSPI SRAM/PSRAM/FRAM/etc. This could either be a non-populated SOIC-8 pad, a SOIC-8 DIP adapter footprint, or some kind of PMOD connector
• It might be desirable to use an external port expander, shift register, or similar to provide the 8x GO signals. This will help save pins on the Feather connector.

Edit:

I wanted to add a couple notes.

1. I'd like to be able to order these boards relatively cheaply through a service like JLCPCB or OshPark
2. I'd like these boards to be mostly through-hole compatible, so that they are easily solderable as kits, OR to be orderable fully populated (e.g. with JLCPCB's assembly service)
3. I am willing to fund the first couple hardware spins (PCBs, Components) for this. Please get confirmation from me directly BEFORE ORDERING if you would like me to pay for this or reimburse you.

The original design for Anachro had multiple SPI lines, which was better suited for the nRF52's muxable pins. For Stargazer, I've ended up using a single shared SPI bus, which means that flexibility matters less than speed.

I'd like to have an Arbitrator with a faster SPI Peripheral, as the nRF52840 has a maximum speed of 8MHz. My current plan is to use one of the following boards:

• Adafruit STM32F405 Feather Express - 42Mbps Max
• WeAct USB-C/Black Pill - 50Mbps Max

This might be easier to do after #5 or #7 have been completed.

I'm also open to suggestions for other boards or MCUs to use instead!

Just some idea: With a few resistors, transistors, and a diode, it would be possible to use a single GPIO pin on the arbitrator to get a transfer request from a device, and accept that request using the same pin, while also controlling the buffer enable line and the chip select of the arbitrator:

Anachro Iris is intended to be the second generation of hardware, succeeding the Anachro Stargazer.

I'd like to rethink how cards are connected here, as a full parallel-connected backplane is not actually fully necessary for an Anachro PC.

Some items I have considered:

• A smaller card connector, allowing for a smaller motherboard
• Potentially a non-card layout, using headers/wires to connect each Card to the Arbitrator (think like an octopus)
• Fewer pins between each card and the backplane. For example, full functionality could be provided with only 8 pins:
  • A single GO line
  • CIPO
  • COPI
  • CSn
  • CLK
  • +5v0 or +3v3
  • GND
  • Reset

There is no ETA for the design of the Iris, and it makes sense to continue prototyping with the Stargazer for now. This issue is for collecting ideas and discussions when it makes sense to iterate.

At the moment, I am not ready to fund the first hardware spins of this, but if you would like to design one of these and would need financial assistance, please get in contact with me.

Currently, the Stargazer is using the RC2014 Backplane 8 as a backplane. I am using this backplane with the following pinout

This works really well, and there is no immediate need to replace this, however if there is interest, the following changes would be nice to have:

• With the current pinout, we could support 1 arbitrator + 8 cards, so 9 slots in total
• It would be nice to have a USB-C power connector with PD support directly, rather than needing a DC barrel jack or external module.
• It could be nice to have a dedicated battery that could be shared with the entire board, providing 3.3v and potentially 5v rail power.
• It would be nice to have slightly more spacing between at least some cards, to allow for things like stacked Featherwings
• It could be nice to have some bus specific items provided by the board, such as:
  • Pull-ups on the GO lines
  • Pull-up on the CSn line
  • Dedicated SWD breakouts to avoid the need for a Debug Card
• Optional but awesome: add a USB hub and DAPLink chips for each card directly, so all cards can be debugged directly through the main USB connection

At the moment, I am not ready to fund the first hardware spins of this, but if you would like to design one of these and would need financial assistance, please get in contact with me.

This issue is similar to #4, however I would also like to have cards that have a low profile socket for the Blue Pill and Black Pill boards.

These can be low cost alternatives to using Adafruit Feather modules.

Edit:

I wanted to add a couple notes.

1. I'd like to be able to order these boards relatively cheaply through a service like JLCPCB or OshPark
2. I'd like these boards to be mostly through-hole compatible, so that they are easily solderable as kits, OR to be orderable fully populated (e.g. with JLCPCB's assembly service)
3. I am willing to fund the first couple hardware spins (PCBs, Components) for this. Please get confirmation from me directly BEFORE ORDERING if you would like me to pay for this or reimburse you.

This issue is similar to #5, however I would also like to have cards that have a low profile socket for the Blue Pill and Black Pill boards.

These can be low cost alternatives to using Adafruit Feather modules.

Edit:

I wanted to add a couple notes.

1. I'd like to be able to order these boards relatively cheaply through a service like JLCPCB or OshPark
2. I'd like these boards to be mostly through-hole compatible, so that they are easily solderable as kits, OR to be orderable fully populated (e.g. with JLCPCB's assembly service)
3. I am willing to fund the first couple hardware spins (PCBs, Components) for this. Please get confirmation from me directly BEFORE ORDERING if you would like me to pay for this or reimburse you.

I have two instances of this PSRAM PMOD breakout module, and I'd like to add support for this as the Shared System Memory on an Arbitrator. This will require:

• Adding a QSPI driver for a chip, likely the nRF52840
• Writing a Rust driver for the chip, with basic read/write functionality
• Writing a sort of "ring file system/allocator" that can be used by the Object Store plane
• Implement the Object Store Plane for Card and Arbitrators
• Modifying or building a new Arbitrator Card that can connect to the PMOD