alvieboy / xtc-base Goto Github PK

Looks like memory transactions may be lost upon SWI or even branching. Transaction shall be allowed to start, even if that requires stalling the pipeline.
This was observed in a few scenarios with SWI return, and also by inspecting code flow after loading from stack.

Delay slot only allows for a 16-bit insn. This is because the write from the BR/JMP needs to immediatly set the register that holds nextPC, and it currently points to +2 to skip the delay slot.
Option is to store temporarly the register address, and only after evaluating the delay slot instruction size, perform that write.
Other option is to enforce only 16-bit delay slots.