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FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network with a Spatiotemporal FPGA Accelerator

This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network with a Spatiotemporal FPGA Accelerator". The paper is available here.

Citation

If you find this work useful, please cite our paper:

@article{li2024firefly,
  title={FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network with a Spatiotemporal FPGA Accelerator},
  author={Li, Jindong and Shen, Guobin and Zhao, Dongcheng and Zhang, Qian and Zeng, Yi},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2024},
  publisher={IEEE}
}

firefly-v2's People

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firefly-v2's Issues

顶层项目文件(`Top.scala`)位置?

您好,想请 顶层项目文件(类似于Top.scala,会导出一个基于SystemVerilog的SoC设计)的位置?

方便的话可否在README中说明?万分感激!

我注意到每个component有自己的main(),是否需要先导出SystemVerilog后手动组织?

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