This is github for Survey for Analog-IC-Design-Automation.
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Review: Machine Learning Techniques in Analog/RF Integrated Circuit Design, Synthesis, Layout, and Test [PDF]
- Engin Afacan, Nuno Lourenço, RicardoMartins, Günhan Dündar, VLSI 2021
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Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review [PDF]
- Morteza Fayazi, Zachary Colter, Ehsan Afshari, and Ronald Dreslinski, IEEE TCAS-I 2021
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Challenges and opportunities toward fully automated analog layout design [PDF]
- Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Nan Sun, and David Z. Pan, JOS 2020
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Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network [PDF]
- Zhengqi Gao, Jun Tao, Fan Yang, Yangfeng su, Dian zhou ,and Xuan Zeng, ICCAD 2019
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Co-learning Bayesian model fusion: Efficient performance modeling of analog and mixed-signal circuits using side information [PDF]
- Fa Wang, Manzil Zaheer, Xin Li, Jean-Olivier Plouchart, and Alberto Valdes-Garcia, ICCAD, 2015
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Efficient hierarchical performance modeling for integrated circuits via Bayesian co-learning [PDF]
- Mohamad Alawieh, Fa Wang, and Xin Li, DAC 2017
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S2-PM semi-supervised learning for efficient performance modeling of analog and mixed signal circuits [PDF]
- Mohamed Baker Alawieh, Xiyuan Tang, and David Z. Pan, ASPDAC 2019
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Rethinking sparsity in performance modeling for analog and mixed circuits using spike and slab models [PDF]
- Mohamed Baker Alawieh, Sinead A. Williamson, and David Z. Pan, DAC 2019
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Modelling a simple current to voltage converter using ANN [PDF]
- Veepsa Bhatia, Kriti Gupta, Nidhi Batra, Neeta Pandey, ICPEICES 2016
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Modelling and design of inverter threshold quantization based current comparator using artificial neural networks [PDF]
- Veepsa Bhatia, Neeta Pandey, Asok Bhattacharyya, International Journal of Electrical and Computer Engineering (IJECE) 2016
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Artificial Neural Network Assisted Analog IC Sizing Tool [PDF]
- Gamze İslamoğlu, Tuğberk Oğulcan Çakici, Engin Afacan, Günhan Dündar, SMACD 2019
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An efficient Bayesian optimization approach for automated optimization of analog circuits [PDF]
- Wenlong Lyu, Pan Xue, Fan Yang, Changhao Yan, Zhiliang Hong, Xuan Zeng, Dian Zhou, IEEE TCAS-I, 2018
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Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design [PDF]
- Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, PMLR,2018
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Multi-objective bayesian optimization for analog/rf circuit synthesis [PDF]
- Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, and Xuan Zeng, DAC 2018
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Bayesian optimization approach for analog circuit synthesis using neural network [PDF]
- Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, DATE 2019
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Analog circuit generator based on deep neural network enhanced combinatorial optimization [PDF]
- Kourosh Hakhamaneshi, Nick Werblun, Pieter Abbeel, and Vladimir, DAC 2019
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Smart-MSP: A self-adaptive multiple starting point optimization approach for analog circuit synthesis [PDF]
- Yishi Yang, Hengliang Zhu, Zhaori Bi, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017
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Learning to design circuits [PDF]
- Hanrui Wang, Jiacheng Yang, Hae-Seung Lee, Song Han, arxiv 2020
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A seizure-detection IC employing machine learning to overcome data-conversion and analog-processing non-idealities [PDF]
- Jintao Zhang, Liechao Huang, Zhuo Wang, Naveen Verma, CICC 2015
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Prediction of element values of OpAmp for required specifications utilizing deep learning [PDF]
- Nobukazu Takai, Masafumi Fukuda, ISESD 2017
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On the exploration of promising analog ic designs via artificial neural networks [PDF]
- Nuno Lourenço, João Rosa, Ricardo Martins, Helena Aidos; António Canelas, Ricardo Póvoa, Nuno Horta, SMACD, 2018
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RF-LNA circuit synthesis using an array of artificial neural networks with constrained inputs [PDF]
- Etienne Dumesnil, Frederic Nabki, Mounir Boukadoum, ISCAS, 2015
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Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing [PDF]
- N. Lourenço, E. Afacan, R. Martins, F. Passos, A. Canelas, R. Póvoa, N. Horta, G. Dundar, SMCAD, 2019
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Deep reinforcement learning for analog circuit sizing [PDF]
- Zhenxin Zhao, Lihong Zhang, ISCAS 2020
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AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs [PDF]
- Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi, Borivoje Nikolic, DATE 2020
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Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards [PDF]
- Yannick Uhlmann, Michael Essich, Lennart Bramlage, Jürgen Scheible, and Cristóbal Curio, MLCAD 2022
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Domain Knowledge-Infused Deep Learning for Automated Analog/Radio-Frequency Circuit Parameter Optimization [PDF]
- Weidong Cao, Mouhacine Benosman, Xuan Zhang, Rui Ma, DAC 2022
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VLSI Placement Parameter Optimization using Deep Reinforcement Learning [PDF]
- Anthony Agnesina, Kyungwook Chang, and Sung Kyu Lim, ICCAD 2020
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GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning [PDF]
- Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han, DAC 2020
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An efficient learning based approach for performance exploration on analog and RF circuit synthesis [PDF]
- Po-Cheng Pan, Chien-Chia Huang, and Hung-Ming Chen, DAC 2019
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An Analog/RF Circuit Synthesis and Design Assistant Tool for Analog IP: DATA-IP [PDF]
- Ezgi Kaya, Engin Afacan, Gunhan Dundar, SMACD 2018
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Harvesting design knowledge from the internet: High-dimensional performance tradeoff modeling for large-scale analog circuits [PDF]
- Jun Tao, Changhai Liao, Xuan Zeng, Xin Li, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2016
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An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration [PDF]
- Yaping Li, Yong Wang, Yusong Li, Ranran Zhou, Zhaojun Lin, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2020
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S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity [PDF]
- Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan, ASP-DAC 2020
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Analog placement constraint extraction and exploration with the application to layout retargeting. [PDF]
- Biying Xu, Bulent Basaran, Ming Su, and David Z. Pan, ISPD 2018
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Towards decrypting the art of analog layout: Placement quality prediction via transfer learning. [PDF]
- Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan, DATE 2020
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Analog layout synthesis with knowledge mining [PDF]
- Po-Hsun Wu, Mark Po-Hung Lin, Tsung-Yi Ho, ECCTD 2015
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A general approach for identifying hierarchical symmetry constraints for analog circuit layout [PDF]
- Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, and Sachin S. Sapatnekar, ICCAD 2020.
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GANA: Graph convolutional network based automated netlist annotation for analog circuits [PDF]
- Kunal, Kishor and Dhar, Tonmoy and Madhusudan, Meghna and Poojary, Jitesh and Sharma, Arvind and Xu, Wenbin and Burns, Steven M. and Hu, Jiang and Harjani, Ramesh and Sapatnekar, Sachin S., DATE 2020
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Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis [PDF]
- Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan, DAC 2020
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Design Rule Checking with a CNN Based Feature Extractor [PDF]
- Luis Francisco, Tanmay Lagare, Arpit Jain, Somal Chaudhary, Madhura Kulkarni, Divya Sardana, W. Rhett Davis, and Paul Franzon, MLCAD 2020
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MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design [PDF]
- Brett Shook, Prateek Bhansali, Chandramouli Kashyap, Chirayu Amin, Siddhartha Joshi, DAC 2020
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A customized graph neural network model for guiding analog IC placement [PDF]
- Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, and Jiang Hu, ICCAD 2020
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Are Analytical Techniques Worthwhile for Analog IC Placement? [PDF]
- Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu, DATE 2022
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Align: Open-source analog layout automation from the ground up [PDF]
- Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, and Sachin S. Sapatnekar, DAC 2019
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Artificial Neural Networks as an Alternative for Automatic Analog IC Placement [PDF]
- Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins, SMACD 2019
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Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender [PDF]
- António Gusmão, Fábio Passos, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins, ISCAS 2020
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Wellgan: Generative-adversarial-network-guided well generation for analog/mixed-signal circuit layout [PDF]
- Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, and David Z. Pan, DAC 2019
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Two-step RF IC block synthesis with preoptimized inductors and full layout generation in-the-loop [PDF]
- Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Póvoa, António Canela, Elisenda Roca, Rafael Castro-López, Javier Sieiro, Francisco V. Fernandez, Nuno Horta, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2019
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Current-flow and current-density-aware multi-objective optimization of analog IC placement [PDF]
- Ricardo Martins, Ricardo Póvoa, Nuno Lourenço, Nuno Horta, Integration 2016
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Analog placement with current flowand symmetry constraints using PCP-SP [PDF]
- Abhishek Patyal, Po-Cheng Pan, Asha K A, Hung-Ming Chen, Hao-Yu Chi, and Chien-Nan Liu, DAC 2018
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MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence [PDF]
- Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan, ICCAD 2019
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GUI-Enhanced layout generation of ffe sst txs for fast high-speed serial link design [PDF]
- Seungho Han, Sungyu Jeong, Chanho Kim, Hong-June Park, Byungsub Kim, DAC 2020
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BAG2: A process-portable framework for generator-based ams circuit design [PDF]
- Eric Chang, Jaeduk Han, Woorham Bae, Zhongkai Wang, Nathan Narevsky, Borivoje NikoliC, Elad Alon, CICC 2018
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Layout-dependent effects-aware analytical analog placement. [PDF]
- Hung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, I-Peng Wu, and Yao-Wen Chang, DAC 2015
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Hierarchical and analytical placement techniques for high-performance analog circuits [[PDF]](Hierarchical and analytical placement techniques for high-performance analog circuits)
- Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, and David Z. Pan, ISPD 2017
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Device layer-aware analytical placement for analog circuits. [PDF]
- Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, ISPD 2019
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Effective analog/mixed-signal circuit placement considering system signal flow [PDF]
- Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, and David Z. Pan, ICCAD 2020
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Exploring a machine learning approach to performance driven analog IC placement [PDF]
- Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Wenbin Xu, Sachin Sapatnekar, Ramesh Harjani, Jiang Hu, ISVLSI 2020
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From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning [PDF]
- Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Ramesh Harjani, Sandeep Gupta, Mike Shuo-Wei Chen, ICCAD 2021
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A pre-search assisted ILP approach to analog integrated circuit routing [PDF]
- Chia-Yu Wu, Helmut Graeb, Jiang Hu, ICCD 2015
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Reliability-driven power/ground routing for analog ICs [PDF]
- Jing-Wei Lin, Tsung-Yi Ho, and Iris Hui-Ru Jiang, ACM Transactions on Design Automation of Electronic Systems 2012
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Toward silicon-proven detailed routing for analog and mixed-signal circuits [PDF]
- Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, and David Z. Pan, ICCAD 2020
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GeniusRoute: A new analog routing paradigm using generative neural network guidance. [PDF]
- Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan, ICCAD 2019
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Attention Routing: Track-Assignment Detailed Routing Using Attention-Based Reinforcement Learning [PDF]
- Haiguang Liao, Qingyi Dong, Xuliang Dong, Wentai Zhang, Wangyang Zhang, Weiyi Qi, Elias Fallon, Levent Burak Kara, IDETC/DAC 2020
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An all-digital scalable and reconfigurable wide-input range stochastic ADC using only standard cells [[PDF]](An all-digital scalable and reconfigurable wide-input range stochastic ADC using only standard cells.)
- Ahmed Fahmy, Jun Liu, Taewook Kim, Nima Maghari, IEEE Transactions on Circuits and Systems II 2015
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A fully automated verilog-to-layout synthesized ADC demonstrating 56 dB-SNDR with 2 MHz-BW [PDF]
- Allen Waters, Un-Ku Moon, A-SSCC 2015
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A reusable code-based SAR-ADC design with CDAC compiler and synthesizable analog building blocks [PDF]
- Min-Jae Seo, Yi-Ju Roh, Dong-Jin Chang, Wan Kim, Ye-Dam Kim, Seung-Tak Ryu, IEEE Transactions on Circuits and Systems II 2018
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A fully synthesizable distributed and scalable all-digital LDO in 10 nm CMOS [PDF]
- Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi, Muhammad Khellah, James Tschanz, Vivek De, ISSCC 2020
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A 60-fJ/step 11-ENOB VCO-based CTDSM synthesized from digital standard cell library [PDF]
- Shaolan Li, Biying Xu, David Z. Pan, Nan Sun, CICC 2019
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A scaling compatible, synthesis friendly VCO-based delta-sigma ADC design and synthesis methodology [PDF]
- Biying Xu, Shaolan Li, Nan Sun, and David Z. Pan, ADC 2017
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Edge-pursuit comparator: An energy-scalable oscillator collapse-based comparator with application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC [PDF]
- Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David Blaauw, Wanyeong Jung, IEEE Journal of Solid-State Circuits 2017
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A Hybrid Design Automation Tool for SAR ADCs in IoT [PDF]
- Ming Ding; Pieter Harpe; Guibin Chen; Benjamin Busze; Yao-Hong Liu; Christian Bachmann; Kathleen Philips, Arthur van Roermund, IEEE TVLSI 2018
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magical-eda/MAGICAL: Machine Generated Analog IC Layout
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