zilinzhou0102 Goto Github PK
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zilinzhou0102's Projects
axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
biriscv
32-bit Superscalar RISC-V CPU
cache
L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
kianriscv
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
riscv
RISC-V CPU Core (RV32IM)
small-room
a small room of learner
verilog-axi
Verilog AXI components for FPGA implementation
xiangshan
Open-source high-performance RISC-V processor
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