zhl56746 Goto Github PK

100g-fpga-network-stack-core

This repo contains the Limago code

10g_tcpip_files

antikernel-ipcores

FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations

awesome-dv

Awesome ASIC design verification

axi4_master_interconnect_slave

A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple masters arbitration. Simulation waveforms are also included.

corundum

Open source FPGA-based NIC and platform for in-network compute

digitaltrackingcalorimetertoolkit

Toolkit for the Monte Carlo and data analysis for the Digital Tracking Calorimeter project. https://doi.org/10.1016/j.nima.2017.02.007

erbium

Business Rule Engine Hardware Accelerator

eth_vlg

ethernet_mac

Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL

ex2_sitrineo

fifo

Generic FIFO implementation with optional FWFT

fotiaoqiang

佛跳墙官方版本下载页 翻墙 代理 科学上网 外网 加速器 梯子 路由

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

fpga-stack-network

ethernet in fpga

geant4medipix

Pixel based Medipix geometry with digitiser for simulating Monte Carlo and charge transport simulation as well as chip electronics.

huawei_pcmanager_nb

非华为电脑也能使用华为多屏协同了

ipcore

jadepix

Jade Pixel

pcie_adapter_software_using_wdf_and_qt

PCIe driver using WDF

pixel-detector

pkuxiadaq

A general-purpose digital data acquisition system(GDDAQ)

qt-sapidswitch

[Qt] 爱心形状开关，支持手势拖动

qt-showywidgets

[Qt] 个人开发的各种花里胡哨的Qt控件集合

scintillator

sourcesim

A program to simulate electrons and gammas from a radioactive source (e.g. SR-90, Am-241) interacting with pixel sensors. Shielding and triggering can be simulated and the setup (e.g. geometry, materials) can be easily changed.

tcpip_echo

A simple echo app using Xilinx TCP/IP offload engine and the 10G/25G ethernet subsystem for Ultrascale

topmetal_firmware

vcu1525_hls_acceleration_framework_split_xdma

VCU1525_HLS_acceleration_framework_split_xDMA

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server