yudefang Goto Github PK

axi-sdcard-high-speed-controller

A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)

brianhg-ddr3-controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

fft-generator

gem5-src

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

l2-llc-caches

SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol

nyuzi-gpgpu

GPGPU microprocessor architecture

opentitan

OpenTitan: Open source silicon root of trust

riscv-rootfs

checkpoint-fix

sdram-controller

Verilog SDRAM memory controller

xuantie-c910

OpenXuantie - OpenC910 Core