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ahb_master

Generic AHB master stub

amba_axi_ahb_apb

AMBA bus lecture material

arm_amba_design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

books

Awesome Books

cdc

Repository gathering basic modules for CDC purpose

chisel_small_module

chisel hdl small module

cosim_bfm_library

HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI

dma

Open-Source AXI4 DMA Engine in SystemVerilog and Chisel

dma_ahb

AHB DMA 32 / 64 bits

dpi_tutorial

SystemVerilog Direct Programming Interface (DPI) Tutorial

fastvdma

Antmicro's fast, vendor-neutral DMA IP in Chisel

gen_amba_2021

AMBA bus generator including AXI4, AXI3, AHB, and APB

hdlgen

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

introduction-to-soc-design-education-kit

Introduction to SoC Design Education Kit

ralbot-header

:beetle:Generate C/Verilog header file from compiled SystemRDL input

riscv-dma

The 3rd Iteration of the Berkeley RISC-V DMA Accelerator

sifive-blocks

Common RTL blocks used in SiFive's projects

spoon-knife

This repo is for demonstration purposes only. Comments and issues may or may not be responded to.

tempimg_tempimg

the-project-of-verilog

Some design examples of Verilog about digital circuits

verilog.jl

Verilog for Julia

vim_hdl_trace

if use gvim write verilog and systemverilog code. this vim plugin help you. It's similar verdi trace connect.

yqcmail

Config files for my GitHub profile.