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wu-gaoxiang's Projects

16-bits-multi-cycle-cpu icon 16-bits-multi-cycle-cpu

CPU Design project for the course "Application and Design of Digital Logic" at Glasgow College, UESTC .

8-bits-risc-cpu-verilog icon 8-bits-risc-cpu-verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

bicubic-plusplus icon bicubic-plusplus

Bicubic++ (NTIRE @ CVPR 2023, Real Time Super Resolution Track 2 winner)

dive_into_deep_learning icon dive_into_deep_learning

✔️李沐 【动手学深度学习】课程学习笔记：使用pycharm编程，基于pytorch框架实现。

espcn icon espcn

A PyTorch implementation of ESPCN based on CVPR 2016 paper "Real-Time Single Image and Video Super-Resolution Using an Efficient Sub-Pixel Convolutional Neural Network"

h265_decoder icon h265_decoder

H265 decoder write in verilog, verified on Xilinx ZYNQ7035

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