Support memory maps about bitfield HOT 11 OPEN

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From the nRF52833 document:

Where, apropos of nothing, I found this SPI timing diagram:

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Do you have some visually pleasing example of memory map diagram that you like?

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Here's a memory map from the EFM32HG by SiLabs, which is a bit on the advanced side but nicely shows how you'd expand on memory register regions. This is my favourite of the bunch, because of how it visually explains where the "expanded" regions are:

Various 8051 chips also have handy memory maps, and because they're so small they actually specify bitfields within the memory maps:

Here's one of the Nintendo 64, which mostly illustrates how you'd have variable-height regions:

Here's one describing the NES, which is nice because it has two side-by-side memory maps that are independent:

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Example with some paper tear effect.

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I spent a lot of time with the i.MX233 which has a bank of otp fuses. Here's the memory map from the reference manual:

Here's the full memory map, which just has the peripherals listed as "Peripheral Space":

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Necessary modification I see:

• left-sided index must be a settable property of lane
  • may be autofilled via global option for default compact behaviour
  • additional begin & end index needs to be introduced for large adress spaces
  • attributes may be used for this, since they are not compatible with the compact mode
• cage rendering must support multiple options
  • merged option
    • only left/right, starting lane bottom and ending lane top border is drawn. Multiple lanes would be merged to a single thing. Label is only drawn once.
  • no tick option
    • draw no ticks inside the cage
  • crossed out option
    • connecting left,bottom corner with right,upper one
      • for showing non linear behaviour
• some attribute holding a whole new bitfield object
  • will be on the right side of prior bitfield
  • centered to the lane holding the attribute
  • have these "extending" lines from the right corners of cage to the left corners of new bitfield

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@nopeslide good ideas. I would need some sketches of the ideas you have.

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@drom I sketched just the index and sub-bitfield idea

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Discovered in the reference manual of an RZ/T1 -- this has four separate memory spaces, and so there are four columns.

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