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1st-claas

Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

a2o

bextdep

Reference Hardware Implementations of Bit Extract/Deposit Instructions

bluespec_bsv_tutorial

Bluespec BSV HLHDL tutorial

darkriscv

opensouce RISC-V implemented from scratch in one night!

deep-learning-keras-tf-tutorial

Learn deep learning with tensorflow2.0, keras and python through this comprehensive deep learning tutorial series. Learn deep learning from scratch. Deep learning series for beginners. Tensorflow tutorials, tensorflow 2.0 tutorial. deep learning tutorial python.

dnn_tl-v

embeddedlinuxbbb

getting-started-fv

githubgraduation-2021

Join the GitHub Graduation Yearbook and "walk the stage" on June 5.

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

lf-building-a-risc-v-cpu-core

ncgpythoncocotb

Written test for Python + Cocotb QC developer

nexys4ddr

Various projects for the Nexys4DDR board from Digilent

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

pulpino

An open-source microcontroller system based on RISC-V

python-cheatsheet

Comprehensive Python Cheatsheet

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

riscv-compliance

riscv-formal

RISC-V Formal Verification Framework

siliconcompiler

SiliconCompiler is an open source build system that automates translation from source code to silicon.

tlv_flow_lib

Generic transaction flow components (like FIFOs, arbitors, and stall pipelines) for Transaction-Level Verilog

verilogboy

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

warp-v_includes

A companion to /warp-v containing files that are included from /warp-v.